Trenched MOS Gate Controller Rectifier

Abstract

A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.

We claim: 
     
         1 . A semiconductor chip having an asymmetric trench structure, comprising:
 a first trench having semiconductor sidewalls;   a second trench disposed inside the first trench and having dielectric sidewalls and filled with a first conductive material;   the first trench and the second trench being symmetrical with respect to an imaginary plane that runs along the middle of the trenches in parallel to the sidewalls; and   a third trench disposed in the dielectric sidewall and filled with a second conductive material; and;   a conductive film disposed over the third trench and partially over the first trench and the second trench, shorting the first conductive material to the second conductive material.   
     
     
         2 . The semiconductor chip of  claim 1 , in which a second metal layer comprising aluminum covers the conductive film. 
     
     
         3 . A semiconductor chip, comprising:
 a chip surface of epitaxial semiconductor material;   a first trench extending from the chip surface into the epitaxial material with two parallel sidewalls perpendicular to the chip surface;   a dielectric liner disposed on the sidewalls;   a second trench disposed inside the first trench, symmetrical with respect to an imaginary center plane that runs along the middle of the first trench and the second trench and having a length coextensive with the first trench, the second trench filled with a conductive material;   a third trench disposed only in the dielectric liner of one sidewall of the first trench having a length coextensive with the first trench and the second trench, and filled with a conductive material;   a fourth trench disposed adjacent to the first trench, separated by a mesa region, the fourth trench extending from the chip surface into the epitaxial material, with two sidewalls of epitaxial semiconductor material and dielectric material lining the sidewalls;   a fifth trench and a sixth trench, each similar to the third trench, disposed in the dielectric material of a sidewall of the fourth trench, symmetrical with respect to an imaginary plane that runs along the middle of the fourth trench;   the fifth trench and the sixth trench having equal length coextensive with the fourth trench.   
     
     
         4 . The semiconductor chip of  claim 3 , in which the thickness of the dielectric material between a sidewall and the third trench is thinner than the thickness of the dielectric material between an opposite sidewall and the second trench. 
     
     
         5 . The semiconductor chip of  claim 3 , further comprising a seventh trench disposed adjacent to the first trench, separated by a mesa region, extending from the chip surface into the epitaxial material, with two sidewalls of epitaxial semiconductor material and dielectric material lining the sidewalls, free of additional trenches in the dielectric material liner. 
     
     
         6 . The semiconductor chip of  claim 3 , in which the first trench is disposed between at least one termination trench and at least one active trench. 
     
     
         7 . The semiconductor chip of  claim 6 , in which the at least one active trench comprises a plurality of active trenches of equal width and length. 
     
     
         8 . The semiconductor chip of  claim 7 , in which the termination trench is wider than the at least one active trench. 
     
     
         9 . The semiconductor chip of  claim 8 , in which the active trenches are disposed in an area enclosed by the termination trench. 
     
     
         10 . The semiconductor chip of  claim 9 , in which each active trench has a field plate element connected electrically to a first metal layer. 
     
     
         11 . The semiconductor chip of  claim 10 , in which each termination trench has a field plate element isolated electrically from the first metal layer. 
     
     
         12 . The semiconductor chip of  claim 11 , in which each active trench has a gate electrode element connected electrically to a second metal layer. 
     
     
         13 . The semiconductor chip of  claim 2 , further comprising a conductive channel with a bias voltage applied to the conductive material in the third trench. 
     
     
         14 . The semiconductor chip of  claim 2 , in which the aspect ratio of the first trench is not less than 1.5. 
     
     
         15 . The semiconductor chip of  claim 2 , in which the aspect ratio of the first trench is not less than 1.7. 
     
     
         16 . The semiconductor chip of  claim 12  being a rectifier device. 
     
     
         17 . The semiconductor chip of  claim 16 , in which the first metal layer and the second metal layer are the same metal layer.