US2021043753A1PendingUtilityA1
Semiconductor device and method of manufacturing thereof
Est. expiryJun 28, 2038(~11.9 yrs left)· nominal 20-yr term from priority
H10P 50/73H10W 10/011H10W 10/10H10D 64/037H10D 30/024H10D 64/017H10D 84/038H10D 84/0158H10D 84/834H01L 21/31144H01L 29/40117H01L 29/66795H01L 21/762H01L 27/11568H01L 29/66545H01L 27/11565H10B 43/10H10B 43/30
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Claims
Abstract
A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device comprising:
a protrusion which is a part of a semiconductor substrate and selectively protrudes from an upper surface of the semiconductor substrate, and extends in a first direction in a plan view; an element isolation portion formed on the upper surface of the semiconductor substrate and whose upper surface position is lower than a position of an upper surface of the protrusion; an interlayer insulating film formed to cover the protrusion and the element isolation portion; a first opening formed in the interlayer insulating film and opening a part of the protrusion and a part of the element isolation portion and extending in a second direction which is orthogonal to the first direction in a plan view; a first gate electrode formed on the upper surface and a side surface of the protrusion and on the upper surface of the element isolation portion via a first gate insulating film; a second gate electrode formed on the upper surface and the side surface of the protrusion and on the upper surface of the element isolation portion; a first plug being contacted with the first gate electrode on the upper surface of the element isolation portion; and a second plug being contacted with the second gate electrode on the upper surface of the element isolation portion, wherein, in the first direction, a width of the first opening in a region where the first plug is formed and a width of the first opening in a region where the second plug is formed are smaller than ½ of a width of the first opening on the upper surface of the protrusion, respectively.
2 . A semiconductor device according to claim 1 ,
wherein, inside the first opening in the region where the first plug is formed, the first gate insulating film and the first gate electrode are formed, and the second gate insulating film and the second gate electrode are not formed, and wherein, inside the first opening in the region where the second plug is formed, the second gate insulating film and the second gate electrode are formed and the first gate insulating film and the first gate electrode are not formed.
3 . The semiconductor device according to claim 2 , wherein, in the second direction, the first plug is formed on a side opposite to another side on which the second is formed through the protrusion.Join the waitlist — get patent alerts
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