Sample and hold circuit

Abstract

A sample and hold circuit with long hold time. A sample and hold circuit includes an amplifier, a capacitor, a switch, and a sampling network. The capacitor includes a first terminal coupled to an inverting input of the amplifier. The switch includes a first terminal that is coupled to an output of the amplifier, and a second terminal that is coupled to the inverting input of the amplifier. The sampling network is coupled to a non-inverting input of the amplifier.

What is claimed is: 
     
         1 . A sample and hold circuit, comprising:
 an amplifier;   a capacitor comprising a first terminal coupled to an inverting input of the amplifier;   a switch comprising:
 a first terminal coupled to an output of the amplifier; and 
 a second terminal coupled to the inverting input of the amplifier; and 
   a sampling network coupled to a non-inverting input of the amplifier.   
     
     
         2 . The sample and hold circuit of  claim 1 , wherein the switch is a first switch and the sample and hold circuit further comprises a second switch comprising:
 a first terminal coupled to the output of the amplifier; and   a second terminal coupled to a second terminal of the capacitor.   
     
     
         3 . The sample and hold circuit of  claim 1 , wherein:
 the capacitor is a first capacitor;   the switch is a first switch; and   the sampling network comprises:
 a second capacitor comprising a terminal coupled to a non-inverting input of the amplifier; 
 a second switch comprising:
 a first terminal coupled to the terminal of the second capacitor; and 
 a second terminal coupled to a second terminal of the first capacitor; and 
 
 a third switch comprising a terminal coupled to the second terminal of the first capacitor. 
   
     
     
         4 . A sample and hold circuit, comprising:
 an amplifier;   a switch configured to switchable couple an output of the amplifier to an inverting input of the amplifier;   a sampling network coupled to a non-inverting input of the amplifier; and   a capacitor coupled to the inverting input of the amplifier, and configured to store offset voltage of the amplifier.   
     
     
         5 . The sample and hold circuit of  claim 4 , wherein the switch is a first switch and the sample and hold circuit further comprises a second switch configured to couple the output of the amplifier to the capacitor. 
     
     
         6 . The sample and hold circuit of  claim 4 , wherein:
 the capacitor is a first capacitor;   the switch is a first switch; and   the sampling network comprises:
 a sampling capacitor coupled to a non-inverting input of the amplifier; 
 a second switch configured to switchably couple an input terminal to the first capacitor; and 
   
       a third switch configured to switchably couple the first capacitor and the second switch to the sampling capacitor.