Capacitor

Abstract

A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

What is claimed is: 
     
         1 . A capacitor made by a wafer and for being bonded to a printed circuit board, the capacitor including:
 a first base layer;   at least one first insulating elevation portion located above the first base layer;   at least one first electrode layer located above the first insulating elevation portion and having first polarity, wherein the first electrode layer is extended along surface profiles of the first insulating elevation portion to increase its extension length;   at least one second electrode layer located above the first electrode layer and having second polarity, wherein the second electrode layer is extended along surface profiles of the first electrode layer to increase its extension length;   a first electrode pad electrically connected to the first electrode layer; and   a second electrode pad electrically connected to the second electrode layer, wherein   the first electrode pad and the second electrode pad are respectively for being bonded to the printed circuit board; and   the first base layer is provided on the wafer.   
     
     
         2 . The capacitor according to  claim 1 , wherein the at least one first electrode layer includes a plurality of first electrode layers, and the at least one second electrode layer includes a plurality of second electrode layers, wherein the first electrode layers and the second electrode layers are stacked in a staggered manner. 
     
     
         3 . The capacitor according to  claim 1 , wherein the at least one first insulating elevation portion includes a plurality of first insulating elevation portions, and there is an insulating elevation recess situated between adjacent two of the first insulating elevation portions, wherein the first electrode layer is extended further along surface profiles of the insulating elevation recess to increase its extension length. 
     
     
         4 . The capacitor according to  claim 1 , further including:
 a protection layer including a first exposed portion and a second exposed portion, wherein the first electrode pad is at least partly exposed from the first exposed portion, and the second electrode pad is at least partly exposed from the second exposed portion.   
     
     
         5 . The capacitor according to  claim 1 , further including:
 at least one dielectric layer located between the first electrode layer and the second electrode layer, for providing electrical isolation between the first electrode layer and the second electrode layer.   
     
     
         6 . The capacitor according to  claim 5 , further including:
 a first conductive channel extended from the first electrode pad to the first electrode layer, for electrically connecting the first electrode pad to the first electrode layer; and   a second conductive channel extended from the second electrode pad to the second electrode layer, for electrically connecting the second electrode pad to the second electrode layer.   
     
     
         7 . The capacitor according to  claim 1 , wherein the first base layer is silicon substrate, glass substrate or quartz substrate. 
     
     
         8 . The capacitor according to  claim 1 , wherein the capacitor further including an etching stop layer located above the first base layer. 
     
     
         9 . A capacitor made by a wafer and for being bonded to a printed circuit board, the capacitor including:
 a first base layer;   at least one first conductive elevation portion located above the first base layer and having second polarity;   at least one first electrode layer located above the first conductive elevation portion and having first polarity, wherein the first electrode layer is extended along surface profiles of the first conductive elevation portion to increase its extension length;   a first electrode pad electrically connected to the first electrode layer and having the first polarity; and   a second electrode pad electrically connected to the first conductive elevation portion and having the second polarity, wherein   the first electrode pad and the second electrode pad are respectively for being bonded to the printed circuit board; and   the first base layer is provided on the wafer.   
     
     
         10 . The capacitor according to  claim 8 , further including: at least one second electrode layer located above the first electrode layer and electrically connected to the first conductive elevation portion to have the second polarity, wherein the second electrode layer is extended along surface profiles of the first electrode layer to increase its extension length. 
     
     
         11 . The capacitor according to  claim 10 , wherein the at least one first electrode layer includes a plurality of first electrode layers, and the at least one second electrode layer includes a plurality of second electrode layers, wherein the first electrode layers and the second electrode layers are stacked in a staggered manner. 
     
     
         12 . The capacitor according to  claim 9 , wherein the at least one first conductive elevation portion includes a plurality of first conductive elevation portions, and there is an conductive elevation recess situated between adjacent two of the first conductive elevation portions, wherein the first electrode layer is extended further along surface profiles of the conductive elevation recess to increase its extension length. 
     
     
         13 . The capacitor according to  claim 9 , further including:
 a protection layer including a first exposed portion and a second exposed portion, wherein the first electrode pad is at least partly exposed from the first exposed portion, and the second electrode pad is at least partly exposed from the second exposed portion.   
     
     
         14 . The capacitor according to  claim 9 , further including:
 at least one dielectric layer located between the first electrode layer and the first conductive elevation portion, for providing electrical isolation between the first electrode layer and the first conductive elevation portion.   
     
     
         15 . The capacitor according to  claim 14 , further including:
 a first conductive channel extended from the first electrode pad to the first electrode layer, for electrically connecting the first electrode pad to the first electrode layer; and   a second conductive channel extended from the second electrode pad to the first conductive elevation portion, for electrically connecting the second electrode pad to the first conductive elevation portion.   
     
     
         16 . The capacitor according to  claim 9 , wherein the first base layer is silicon substrate, glass substrate or quartz substrate. 
     
     
         17 . The capacitor according to  claim 9 , wherein the capacitor further including an etching stop layer located above the first base layer.