Apparatus with a current-gain layout

Abstract

An apparatus including separate first and second active regions that are physically separate, with each region including one or more sets of doped regions that each define a current channel. The current channels on the first and second active regions are activated by a common gate signal.

I/We claim: 
     
         1 . An apparatus, comprising:
 a first active region including a first set of regions configured to selectively provide a first current channel according to a gate signal;   a second active region including a second set of regions configured to selectively provide a second current channel according to the gate signal, wherein:
 the first and second active regions have same dopants and are physically separate, and 
 the first and second current channels correspond to parallel current flow directions; and 
   conductive structure linearly extending across and electrically connecting matching regions within the first and second sets of regions, wherein the conductive structure linearly extends along a direction orthogonal to the parallel current flow directions.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the first set of regions are configured to selectively provide a first adjacent channel according to the gate signal, wherein the first adjacent channel is (1) physically separate and adjacent to the first current channel and (2) extends along the parallel current flow directions;   the second set of regions are configured to selectively provide a second adjacent channel according to the gate signal, wherein the second adjacent channel is (1) physically separate and adjacent to the second current channel and (2) extends along the parallel current flow directions; and   the conductive structure includes a first linear leg and a second linear leg electrically connecting the first current channel, the second current channel, the first adjacent channel, and the second adjacent channel in parallel, wherein the first linear leg and the second linear leg extend along the direction orthogonal to the extends along the parallel current flow directions.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the first set of regions includes a first source region and/or a first drain region associated with the first current channel;   the second set of regions includes a second source region and/or a second drain region associated with the second current channel; and   the conductive structure includes a linear leg that extends across the first active region and the second active region, wherein the linear leg is directly over and electrically connects either the first and second source regions or the first and second drain regions.   
     
     
         4 . The apparatus of  claim 3 , wherein:
 the first set of regions includes a first gate region configured to receive and operate according to the gate signal; and   the second set of regions includes a second gate region configured to receive and operate according to the gate signal.   
     
     
         5 . The apparatus of  claim 1 , further comprising:
 an isolation mechanism between the first active region and the second active region, wherein the isolation mechanism physically separates the first current channel from the second current channel; and   wherein:   the conductive structure extends across the isolation mechanism.   
     
     
         6 . The apparatus of  claim 5 , wherein the isolation mechanism is a shallow trench isolation (STI) mechanism. 
     
     
         7 . The apparatus of  claim 1 , wherein:
 the first current channel has a first channel width; and   the second current channel has a second channel width different than the first channel width.   
     
     
         8 . The apparatus of  claim 1 , wherein the first current channel has a first channel width and the second current channel has a second channel width equal to the first channel width. 
     
     
         9 . The apparatus of  claim 1 , wherein the first current channel has a first channel width and the second current channel has a second channel width, wherein a sum of the first channel width and the second channel width is a total channel width associated with a source-drain current level for the apparatus. 
     
     
         10 . The apparatus of  claim 1 , further comprising:
 a third active region including a third set of regions configured to selectively provide a third current channel according to the gate signal, wherein:
 the third active region has the same dopant as the first and second active regions and is physically separate from the first and second active regions, and 
 the third current channel extends parallel to the parallel current flow directions; and 
   wherein:   the conductive structure linearly extends across the third active region and electrically connects matching regions within the first, second and third sets of regions.   
     
     
         11 . The apparatus of  claim 1 , wherein the first active region, the second active region, and the conductive structure comprise a transistor device. 
     
     
         12 . The apparatus of  claim 11 , wherein the transistor device comprises a data input buffer of the DRAM device. 
     
     
         13 . The apparatus of  claim 12 , wherein the transistor device comprises an amplifier circuit in the data input buffer. 
     
     
         14 . The apparatus of  claim 1 , wherein selectively providing the first and second current channels includes activating the first and second current channels in response to the gate signal. 
     
     
         15 . An apparatus, comprising:
 a first active region comprising (1) a first set of regions cooperating with each other to define a first current channel and (2) a second set of regions cooperating with each other to define a second current channel;   a second active region comprising (1) a third set of regions cooperating with each other to define a third current channel and (2) a fourth set of regions cooperating with each other to define a fourth current channel, the second active region being isolated from the first active region, wherein the first, second, third, and fourth current channels extend along a first direction;   a gate electrode comprising first and second fingers, the first finger extending along a second direction and over the first and third current channels, and the second finger extending along the second direction and over the second and fourth current channels;   a first electrode comprising third and fourth fingers, the third finger extending in the second direction and defining ends of the first and third current channels, the fourth finger extending in the second direction and defining ends of the second and fourth current channels; and   a second electrode comprising a fifth finger, the fifth finger extending in the second direction and defining opposing ends of the first, second, third, and/or fourth current channels.   
     
     
         16 . The apparatus of  claim 15 ,
 wherein regions in each of the first, second, third, and fourth sets of regions are arranged along the first direction;   wherein first matching regions in the first and third sets of regions are arranged along a first line that extends along the second direction; and   wherein second matching regions in the second and fourth sets of regions are arranged along a second line that extends along the second direction.   
     
     
         17 . The apparatus of  claim 15 , wherein the first, second, third, and fourth sets of regions each include a source region, a gate region, and/or a drain region. 
     
     
         18 . The apparatus of  claim 15 , wherein the first, second, third, and fourth current channels are activated according to a gate signal. 
     
     
         19 . The apparatus of  claim 15 , wherein the second active region is isolated from the first active region by a shallow trench isolation (STI). 
     
     
         20 . The apparatus of  claim 16 , wherein the first electrode serves as a source electrode and the second electrode serves as a drain electrode.