Avoid cache lookup for cold cache

Abstract

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

1 - 20 . (canceled) 
     
     
         21 . An apparatus comprising:
 a processor to:
 receive, in a graphics pipeline, a cache access request from a requestor, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and 
 determine whether the cache set associated with the cache set identifier is in an inaccessible state or an invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to:
 terminate the cache access request. 
 
   
     
     
         22 . The apparatus of  claim 21 , the processor to:
 retrieve a cache state tag associated with the cache set; and   determine a value of the cache state tag.   
     
     
         23 . The apparatus of  claim 22 , the processor to determine whether the cache set is in at least one of a cold state or an invalid state. 
     
     
         24 . The apparatus of  claim 21 , the processor to:
 launch a memory access request for the requested data from a memory module coupled to the cache.   
     
     
         25 . The apparatus of  claim 24 , the processor to:
 return the requested data to the requestor.   
     
     
         26 . The apparatus of  claim 21 , the processor to:
 determine whether the graphics pipeline is empty; and   in response to a determination that the graphics pipeline is empty, to:
 terminate the cache access request. 
   
     
     
         27 . The apparatus of  claim 21 , the processor to:
 determine whether the graphics pipeline is includes only read accesses; and   in response to a determination that the graphics pipeline includes only read accesses, to:
 terminate the cache access request. 
   
     
     
         28 . An electronic device, comprising:
 a processor having one or more processor cores, the processor to:
 receive, in a graphics pipeline, a cache access request from a requestor, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and 
 determine whether the cache set associated with the cache set identifier is in an inaccessible state or an invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to: 
 terminate the cache access request; and 
   a computer readable memory communicatively coupled to the processor.   
     
     
         29 . The electronic device of  claim 28 , the processor to:
 retrieve a cache state tag associated with the cache set; and   determine a value of the cache state tag.   
     
     
         30 . The electronic device of  claim 29 , the processor to determine whether the cache set is in at least one of a cold state or an invalid state. 
     
     
         31 . The electronic device of  claim 28 , the processor to:
 launch a memory access request for the requested data from a memory module coupled to the cache.   
     
     
         32 . The electronic device of  claim 31 , the processor to:
 return the requested data to the requestor.   
     
     
         33 . The electronic device of  claim 29 , the processor to:
 determine whether the graphics pipeline is empty; and   in response to a determination that the graphics pipeline is empty, to:
 terminate the cache access request. 
   
     
     
         34 . The electronic device of  claim 28 , the processor to:
 determine whether the RMW pipeline is includes only read accesses; and   in response to a determination that the RMW pipeline includes only read accesses, to:
 terminate the cache access request. 
   
     
     
         35 . A method comprising:
 receiving, in a graphics pipeline, a cache access request from at least one of the plurality of graphics processing cores, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and   terminating the cache access request in response to a determination that the cache set associated with the cache set identifier is in an inaccessible state or an invalid state.   
     
     
         36 . The method of  claim 35 , further comprising:
 retrieving a cache state tag associated with the cache set; and   determining a value of the cache state tag.   
     
     
         37 . The method of  claim 36 , further comprising determining whether the cache set is in at least one of a cold state or an invalid state. 
     
     
         38 . The method of  claim 35 , further comprising:
 launching a memory access request for the requested data from a memory module coupled to the cache.   
     
     
         39 . The method of  claim 38 , further comprising:
 returning the requested data to the requestor.   
     
     
         40 . The method of  claim 35 , further comprising:
 determining whether the graphics pipeline is empty; and   in response to a determination that the graphics pipeline is empty, terminating the cache access request.   
     
     
         41 . The method of  claim 35 , further comprising:
 determining whether the graphics pipeline is includes only read accesses; and   in response to a determination that the graphics pipeline includes only read accesses, terminating the cache access request.   
     
     
         42 . One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
 receive, in a graphics pipeline, a cache access request from at least one of the plurality of graphics processing cores, wherein the cache access request comprises a cache set identifier associated with requested data in a cache set; and   terminate the cache access request in response to a determination that the cache set associated with the cache set identifier is in an inaccessible state or an invalid state.   
     
     
         43 . The non-transitory computer-readable medium of  claim 42 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 retrieve a cache state tag associated with the cache set; and   determine a value of the cache state tag.   
     
     
         44 . The non-transitory computer-readable medium of  claim 43 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to determine whether the cache set is in at least one of a cold state or an invalid state. 
     
     
         45 . The non-transitory computer-readable medium of  claim 42 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 launch a memory access request for the requested data from a memory module coupled to the cache.   
     
     
         46 . The non-transitory computer-readable medium of  claim 45 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 return the requested data to the requestor.   
     
     
         47 . The non-transitory computer-readable medium of  claim 42 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 determine whether the graphics pipeline is empty; and   in response to a determination that the graphics pipeline is empty, to:
 terminate the cache access request. 
   
     
     
         48 . The non-transitory computer-readable medium of  claim 42 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 determine whether the graphics pipeline is includes only read accesses; and   in response to a determination that the graphics pipeline includes only read accesses, to:
 terminate the cache access request.