US2021028059A1PendingUtilityA1

Method for Forming a Buried Metal Line in a Semiconductor Substrate

Assignee: IMEC VZWPriority: Jul 24, 2019Filed: Jul 21, 2020Published: Jan 28, 2021
Est. expiryJul 24, 2039(~13 yrs left)· nominal 20-yr term from priority
H10W 20/427H10W 20/20H10W 20/021H10D 84/0158H10D 84/0149H10D 84/038H01L 21/76847H01L 21/76855H01L 21/76831
56
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for forming a buried metal line in a semiconductor substrate, the method comprising:
 forming, in the semiconductor substrate and at a level below a base of each semiconductor structure, a trench between a pair of semiconductor structures that protrude from the semiconductor substrate;   selectively depositing a metal line material in the trench to thereby form a metal line in the trench; and   embedding the pair of semiconductor structures in an insulating layer.   
     
     
         2 . The method according to  claim 1 , further comprising, prior to selectively depositing the metal line material in the trench:
 forming a barrier layer in the trench, wherein the barrier layer is configured to promote selective growth of the metal material in the trench.   
     
     
         3 . The method according to  claim 2 , wherein the barrier layer comprises a silicide. 
     
     
         4 . The method according to  claim 3 , wherein forming of the barrier layer comprises:
 depositing a silicide metal in the trench;   annealing the silicide metal to form the silicide; and   removing the remaining silicide metal.   
     
     
         5 . The method according to  claim 3 , wherein a height of the metal line exceeds a depth of the trench. 
     
     
         6 . The method according to  claim 3 , wherein the metal line corresponds to a buried power rail. 
     
     
         7 . The method according to  claim 3 , wherein the pair of semiconductor structures are formed by a pair of semiconductor fins. 
     
     
         8 . The method according to  claim 2 , wherein a height of the metal line exceeds a depth of the trench. 
     
     
         9 . The method according to  claim 2 , wherein the metal line corresponds to a buried power rail. 
     
     
         10 . The method according to  claim 2 , wherein the pair of semiconductor structures are formed by a pair of semiconductor fins. 
     
     
         11 . The method according to  claim 1 , wherein forming of the trench comprises:
 forming a spacer on sidewall surfaces of the pair of semiconductor structures, wherein the spacer is configured to mask the sidewall surfaces; and   etching the trench in the semiconductor substrate.   
     
     
         12 . The method according to  claim 11 , wherein selectively depositing the metal line material in the trench comprises:
 depositing the metal line material in the trench until the metal line material is at least partially above the pair of semiconductor structures; and   subsequently etching back the deposited metal material to a level at or above the respective bases of the pair of semiconductor structures.   
     
     
         13 . The method according to  claim 12 , wherein a height of the metal line exceeds a depth of the trench. 
     
     
         14 . The method according to  claim 11 , wherein selectively depositing the metal line material comprises:
 depositing the metal line material in the trench until the metal line material is at least partially above the pair of semiconductor structures; and   subsequently removing the spacer to define the metal line.   
     
     
         15 . The method according to  claim 11 , wherein a height of the metal line exceeds a depth of the trench. 
     
     
         16 . The method according to  claim 11 , wherein the metal line corresponds to a buried power rail. 
     
     
         17 . The method according to  claim 11 , wherein the pair of semiconductor structures are formed by a pair of semiconductor fins. 
     
     
         18 . The method according to  claim 1 , wherein a height of the metal line exceeds a depth of the trench. 
     
     
         19 . The method according to  claim 1 , wherein the metal line corresponds to a buried power rail. 
     
     
         20 . The method according to  claim 1 , wherein the pair of semiconductor structures are formed by a pair of semiconductor fins.

Join the waitlist — get patent alerts

Track US2021028059A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.