Methods and apparatus for an amplifier circuit

Abstract

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may provide a first cross-connect circuit responsive to a first clock signal having a first phase and the third clock signal having a third phase. The amplifier circuit may provide a second cross-connect circuit responsive to a second clock signal having a second phase and a fourth clock signal having a fourth phase. The clock signals have a same frequency with offset phases.

1 . An amplifier, comprising:
 a first cross-connect circuit responsive to a first clock signal having a first phase and a third clock signal having a third phase and configured to receive a first input signal and a second input signal;   a second cross-connect circuit responsive to a second clock signal having a second phase and a fourth clock signal having a fourth phase;   an input stage circuit connected between the first cross-connect circuit and the second cross-connect circuit; and   an output stage circuit connected to an output terminal of the second cross-connect circuit and configured generate an output voltage;   wherein:
 at a first time, the first and second clock signals have a first signal level; 
 at a second time, the first, second, third, and fourth signals have a second signal level; and 
 at a third time, the third and fourth clock signals have the first signal level and the first and second clock signals have the second signal level. 
   
     
     
         2 . The amplifier according to  claim 1 , wherein:
 each of the first, second, third, and fourth phases are offset from each other; and   the first, second, third, and fourth clock signals have a same frequency.   
     
     
         3 . The amplifier according to  claim 1 , wherein the first cross-connect circuit comprises:
 a first switch responsive to the first clock signal;   a second switch in parallel with the first switch and responsive to the third clock signal;   a third switch in series with the first switch and responsive to the third clock signal; and   a fourth switch in series with the second switch and responsive to the first clock signal.   
     
     
         4 . The amplifier according to  claim 3 , wherein:
 the first cross-connect circuit comprises a third node located between the first and third switches and a fourth node located between the second and fourth switches; and   the input stage circuit comprises a differential transistor pair comprising a first transistor and a second transistor, wherein the first transistor is connected to the third node and the second transistor is connected to the fourth node.   
     
     
         5 . The amplifier according to  claim 1 , where the second cross-connect circuit comprises:
 a fifth switch responsive to the second clock signal;   a sixth switch in parallel with the fifth switch and responsive to the fourth clock signal;   a seventh switch in series with the fifth switch and responsive to the fourth clock signal; and   an eighth switch in series with the sixth switch and responsive to the second clock signal.   
     
     
         6 . The amplifier according to  claim 1 , wherein the input stage circuit is responsive to a first bias voltage and a second bias voltage. 
     
     
         7 . The amplifier according to  claim 6 , wherein the amplifier further comprises a voltage adjustment circuit connected to the input stage circuit and responsive to a third bias voltage. 
     
     
         8 . A method for operating a system having an amplifier with a first circuit, a second circuit, and a third circuit, comprising:
 generating:   a first clock signal having a first phase;   a second clock signal having a second phase;   a third clock signal having a third phase; and   a fourth clock signal having a fourth phase;   wherein:
 at a first time, the first and second clock signals have a first signal level; 
 at a second time, the first, second, third, and fourth signals have a second signal level; and 
 at a third time, the third and fourth clock signals have the first signal level and the first and second clock signals have the second signal level; 
   operating the first circuit according to the first clock signal and the third clock signal; and   operating the second circuit according to the second clock signal and the fourth clock signal.   
     
     
         9 . The method according to  claim 8 , wherein the first, second, third, and fourth clock signals are generated based on a first reference clock signal. 
     
     
         10 . The method according to  claim 9 , further comprising operating the third circuit according to a second reference clock signal. 
     
     
         11 . The method according to  claim 10 , wherein the first reference clock signal is proportional to the second reference clock signal by a factor of 1/N, where N is a natural number. 
     
     
         12 . The method according to  claim 8 , wherein:
 each of the first, second, third, and fourth phases are offset from each other; and   the first, second, third, and fourth clock signals have a same frequency.   
     
     
         13 . The method according to  claim 8 , further comprising operating the amplifier according to a first bias voltage, a second bias voltage, and a third bias voltage. 
     
     
         14 . A system, comprising:
 a clock generator configured to generate:
 a first clock signal having a first phase; 
 a second clock signal having a second phase; 
 a third clock signal having a third phase; and 
 a fourth clock signal having a fourth phase;
 wherein: 
 at a first time, the first and second clock signals have a first signal level; 
 at a second time, the first, second, third, and fourth signals have a second signal level; and 
 at a third time, the third and fourth clock signals have the first signal level and the first and second clock signals have the second signal level; 
 
   an amplifier configured to generate an output signal in response to the first, second, third, and fourth clock signals; and   an analog-to-digital converter (ADC) connected to the amplifier configured to convert the output voltage to a digital signal.   
     
     
         15 . The system according to  claim 14 , wherein the clock generator generates the first, second, third, and fourth clock signals based on a reference clock signal. 
     
     
         16 . The system according to  claim 15 , wherein:
 the ADC is responsive to an ADC clock; and   the reference clock signal is proportional to the ADC clock by a factor of 1/N, where N is a natural number.   
     
     
         17 . The system according to  claim 14 , wherein:
 each of the first, second, third, and fourth phases are offset from each other; and   the first, second, third, and fourth clock signals have a same frequency.   
     
     
         18 . The system according to  claim 14 , wherein the amplifier comprises:
 a first cross-connect circuit comprising:
 a first switch responsive to the first clock signal; 
 a second switch in parallel with the first switch and responsive to the third clock signal; 
 a third switch in series with the first switch and responsive to the third clock signal; and 
 a fourth switch in series with the second switch and responsive to the first clock signal; and 
   a second cross-connect circuit comprises:
 a fifth switch responsive to the second clock signal; 
 a sixth switch in parallel with the fifth switch and responsive to the fourth clock signal; 
 a seventh switch in series with the fifth switch and responsive to the fourth clock signal; and 
 an eighth switch in series with the sixth switch and responsive to the second clock signal. 
   
     
     
         19 . The system according to  claim 18 , wherein the amplifier further comprises:
 an input stage circuit connected to the first cross-connect circuit and responsive to a first bias voltage and a second bias voltage; and   an output stage circuit connected to an output terminal of the second cross-connect circuit and configured to generate the output voltage.   
     
     
         20 . The system according to  claim 19 , wherein the amplifier further comprises a voltage adjustment circuit connected to the input state circuit and responsive to a third bias voltage.