Shield gate mosfet and method for fabricating the same
Abstract
A shield gate MOSFET includes an epitaxial layer having a first conductivity type, a plurality of trenches in the epitaxial layer, a shield gate disposed in the trenches, a control gate on the shield gate in the trenches, an insulating layer between the shield gate and the epitaxial layer, a gate oxide layer between the control gate and the epitaxial layer, an inter-gate oxide layer between the shield gate and the control gate, a first doped region in the epitaxial layer at the bottom of the trenches, and a second doped region between the bottom of the trenches and the first doped region. The first doped region has a second conductivity type, and the second doped region has the first conductivity type, and thus the leakage path may be reduced in the presence of the second doped region so as to improve breakdown voltage.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A shield gate MOSFET, comprising:
an epitaxial layer having a first conductivity type; a plurality of trenches formed in the epitaxial layer; a shield gate disposed in the plurality of trenches; a control gate disposed on the shield gate in the plurality of trenches; an insulating layer disposed between the shield gate and the epitaxial layer; a gate oxide layer disposed between the control gate and the epitaxial layer; an inter-gate oxide layer disposed between the shield gate and the control gate; and a first doped region and a second doped region disposed in the epitaxial layer at a bottom of the trenches, and the second doped region is located between the shield gate and the first doped region, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type.
2 . The shield gate MOSFET of claim 1 , wherein the first conductivity type is N type and the second conductivity type is P type.
3 . The shield gate MOSFET of claim 1 , wherein the first conductivity type is P type and the second conductivity type is N type.
4 . The shield gate MOSFET of claim 1 , wherein a top surface of the shield gate covered by the inter-gate oxide layer has rounded corners.
5 . The shield gate MOSFET of claim 1 , further comprising a source region disposed on a surface of the epitaxial layer, and a doping concentration of the second doped region is less than a doping concentration of the source region.
6 . The shield gate MOSFET of claim 1 , wherein a doping concentration of the first doped region is a uniform concentration.
7 . The shield gate MOSFET of claim 1 , wherein the plurality of trenches further extends to a connecting region of the epitaxial layer, the shield gate is extended into the plurality of trenches in the connecting region, and the shield gate MOSFET further comprises a protruding portion in the trenches of the connecting region as a contact electrically connected to the shield gate.
8 . The shield gate MOSFET of claim 7 , wherein the control gate is not extended to the connecting region.
9 . A method for fabricating a shield gate MOSFET, comprising:
forming an epitaxial layer, wherein the epitaxial layer has a first conductivity type; forming a plurality of trenches in the epitaxial layer; forming a first doped region and a second doped region in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type; and forming a MOSFET having a shield gate in each of the trenches.
10 . The method for fabricating the shield gate MOSFET of claim 9 , wherein the first conductivity type is N type and the second conductivity type is P type.
11 . The method for fabricating the shield gate MOSFET of claim 9 , wherein the first conductivity type is P type and the second conductivity type is N type.
12 . The method for fabricating the shield gate MOSFET of claim 9 , wherein the step of forming the MOSFET having the shield gate comprises:
forming an insulating layer on a surface of the epitaxial layer in each of the trenches; forming a conductive layer on the insulating layer in each of the trenches; removing a portion of the conductive layer to form the shield gate and expose a portion of the insulating layer; removing the exposed insulating layer; forming an inter-gate oxide layer and a gate oxide layer in the trenches, wherein the inter-gate oxide layer covers a top surface of the shield gate, and the gate oxide layer covers a surface of the epitaxial layer; and forming a control gate on the inter-gate oxide layer in the plurality of trenches.
13 . The method for fabricating the shield gate MOSFET of claim 12 , further comprising, after removing the portion of the conductive layer and the exposed insulating layer: rounding the top surface of the shield gate.
14 . The method for fabricating the shield gate MOSFET of claim 9 , further comprising forming a source region on a surface of the epitaxial layer, and a doping concentration of the second doped region is less than a doping concentration of the source region.
15 . The method for fabricating the shield gate MOSFET of claim 9 , wherein a doping concentration of the first doped region is a uniform concentration.
16 . The method for fabricating the shield gate MOSFET of claim 12 , wherein the epitaxial layer comprises a connecting region, and when the plurality of trenches are formed in the epitaxial layer, the plurality of trenches are extended to the connecting region, and before the step of removing the portion of the conductive layer, a protective layer is formed on the connecting region to keep the conductive layer in the connecting region.Join the waitlist — get patent alerts
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