Receiver with selectable digital equalization filter options

Abstract

A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.

What is claimed is: 
     
         1 . A device, comprising:
 a receiver having:
 analog front-end circuitry; and 
 a digital signal processing (DSP) circuit, wherein the DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform equalization operations based on the selected filter option, and wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths. 
   
     
     
         2 . The device of  claim 1 , wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on an automatic gain control index value and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths. 
     
     
         3 . The device of  claim 1 , wherein the plurality of DEQ filter options are based on an odd tap symmetric finite impulse response (FIR) filter with selectable coefficients. 
     
     
         4 . The device of  claim 1 , wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a sweeping operation that determines which of a plurality of different sets of DEQ filter coefficients optimizes a performance metric. 
     
     
         5 . The device of  claim 1 , wherein the performance metric is at least one of a decision feedback equalizer (DFE) coefficient metric, a mean-square-error (MSE) noise metric, and a pre-cursor value. 
     
     
         6 . The device of  claim 1 , wherein the selected DEQ filter is configured to run at one sample per symbol. 
     
     
         7 . A digital signal processing (DSP) circuit, comprising:
 a digital equalizer (DEQ) filter with selectable coefficients;   a decision circuit coupled to the DEQ filter;   a decision-feedback equalizer (DFE) circuit coupled to the DEQ filter;   a gain loop circuit coupled to the DEQ filter;   a clock recovery circuit coupled to the decision circuit; and   a controller coupled to the DEQ filter, wherein the controller is configured to select the coefficients for the DEQ filter based on at least one selection criterion.   
     
     
         8 . The DSP circuit of  claim 7 , wherein the DEQ filter is an odd tap symmetric finite impulse response (FIR) filter, and wherein the at least one selection criterion comprises a channel length estimate. 
     
     
         9 . The DSP circuit of  claim 7 , wherein the at least one selection criterion comprises an automatic gain control index value. 
     
     
         10 . The DSP circuit of  claim 7 , wherein the at least one selection criterion comprises a performance metric based on a sweeping operation that tests different sets of DEQ filter coefficients. 
     
     
         11 . The DSP circuit of  claim 9 , wherein the performance metric is at least one of a decision feedback equalizer (DFE) coefficient metric, a mean-square-error (MSE) noise metric, and a pre-cursor value. 
     
     
         12 . The DSP circuit of  claim 7 , wherein the controller is configured to calibrate the performance metric based on scaling a mean-square-error (MSE) threshold. 
     
     
         13 . A method, comprising:
 receiving an input signal;   filtering the input signal using an analog filter system;   converting an output of the analog filter system to a digital signal;   selecting one of a plurality of digital equalization (DEQ) filter options; and   filtering the digital signal based on the selected DEQ filter option.   
     
     
         14 . The method of  claim 13 , wherein selecting one of the plurality of DEQ filter options comprises comparing a channel length estimate to an indexed DEQ filter coefficient table. 
     
     
         15 . The method of  claim 13 , wherein selecting one of the plurality of DEQ filter options comprises comparing an automatic gain control value to an indexed DEQ filter coefficient table. 
     
     
         16 . The method of  claim 13 , wherein selecting one of the plurality of DEQ filter options comprises testing a plurality of different sets of DEQ filter coefficients and selecting a set of DEQ filter coefficients that result in a performance metric being within a threshold. 
     
     
         17 . The method of  claim 16 , wherein the performance metric is at least one of a decision feedback equalizer (DFE) coefficient metric and a mean-square-error (MSE) noise metric. 
     
     
         18 . The method of  claim 16 , wherein the performance metric is a pre-cursor value that correlates a delayed slicer error with a current slicer output.