3D Integrated Circuit and Methods of Forming the Same

Abstract

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;   a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;   a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; and   a dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first dielectric layer has a porosity of less than about 5%. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG). 
     
     
         6 . The semiconductor device of  claim 1 , wherein the second dielectric layer has a porosity of between about 5% and about 40%. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first contact comprises a conductive barrier layer, the conductive barrier layer comprising titanium, titanium nitride, tantalum, or tantalum nitride. 
     
     
         8 . A semiconductor device comprising:
 a substrate; and   a contact structure over the substrate, the contact structure comprising:
 a first layer comprising a first conductive material; 
 a second layer comprising the first conductive material and a first dielectric material; 
 a third layer comprising the first conductive material and a second dielectric material, the second dielectric material having a larger porosity than the first dielectric material, and wherein the second layer is located between the first layer and the third layer; and 
 a fourth layer comprising the first conductive material and a first barrier layer, wherein the first conductive material is planar with the first barrier layer along a surface facing away from the substrate. 
   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first dielectric material has a porosity of less than about 5%. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the second dielectric material has a porosity of greater than about 5% and less than about 40%. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the first barrier layer is fusion bonded to a second barrier layer. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the first conductive material is metal-to-metal bonded to a second conductive material. 
     
     
         13 . The semiconductor device of  claim 8 , wherein the first dielectric material comprises un-doped silicate glass (USG). 
     
     
         14 . The semiconductor device of  claim 8 , wherein the first barrier layer comprises a siloxane-based polymer. 
     
     
         15 . A semiconductor device comprising:
 a semiconductor substrate with an active device layer;   a metallization layer overlying the semiconductor substrate;   a first layer overlying the metallization layer;   a contact isolation structure overlying the first layer, the contact isolation structure comprising:
 a first dielectric layer in physical contact with the first layer; 
 a second dielectric layer in physical contact with the first dielectric layer, the second dielectric layer having a larger porosity than the first dielectric layer; 
 a barrier layer in physical contact with the second dielectric layer, wherein each of the first dielectric layer, the second dielectric layer, and the barrier layer have a planar surface facing away from the semiconductor substrate; and 
   a conductive contact extending through the contact isolation structure and the first layer to make physical contact with the metallization layer, the conductive contact having straight sidewalls.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the straight sidewalls are perpendicular to the semiconductor substrate. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the straight sidewalls are tilted with respect to the semiconductor substrate. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the barrier layer has a thickness of less than about 1 μm. 
     
     
         19 . The semiconductor device of  claim 15 , wherein the barrier layer comprises silicon oxynitride. 
     
     
         20 . The semiconductor device of  claim 15 , wherein the second dielectric layer has a k value of between about 2.5 and 3.0.