Internally stacked npn with segmented collector

Abstract

An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

1 - 19 : (canceled) 
     
     
         20 . An electronic device, comprising:
 an emitter region, a collector region and a base region formed within a semiconductor substrate having a first conductivity type;   a deep-doped region having a second opposite conductivity type, the deep-doped region extending to a buried layer having the second conductivity type that extends under the emitter region, the collector region and the base region;   an array of deep trench islands within the deep-doped region, the deep trench islands conductively isolated from the buried layer and located between the collector region and the emitter region such that current between the connector region and the emitter region passes between the deep trench islands; and   the collector region includes collector contacts arranged as a plurality of linear arrays, each linear array separated from a nearest-neighbor linear array by a dielectric isolation structure.   
     
     
         21 . The device of  claim 20 , wherein the linear arrays are aligned along a direction of current between the emitter region and the collector region. 
     
     
         22 . The device of  claim 20 , further wherein the linear arrays of collector contacts are arranged such that current between each linear array and the emitter region follows a direct path between corresponding pairs of nearest-neighbor deep trench islands. 
     
     
         23 . The device of  claim 20 , wherein the linear arrays are aligned along a direction of current between the emitter region and the collector region. 
     
     
         24 . The device of  claim 20 , wherein the deep trench islands each include a polysilicon core that conductively connects to the semiconductor substrate below the buried layer. 
     
     
         25 . The device of  claim 20 , wherein the emitter includes a doped region of the second conductivity type located within a well region of the first conductivity type. 
     
     
         26 . The device of  claim 20 , wherein the base region includes a well region of the first conductivity type that surrounds a well region of the second conductivity type. 
     
     
         27 . The device of  claim 20 , wherein the collector region includes a well region of the first second conductivity type surrounded by a well region of the second conductivity type. 
     
     
         28 . The device of  claim 20 , wherein the deep trench islands each include a conductive core laterally surrounded by an insulting liner. 
     
     
         29 . The device of  claim 20 , wherein the first conductivity type is P-type and the second conductivity type is N-type. 
     
     
         30 . An electronic device, comprising:
 an emitter region, a collector region and a base region formed within a semiconductor substrate having a first conductivity type;   a deep-doped region having a second opposite conductivity type, the deep-doped region extending to a buried layer having the second conductivity type that extends under the emitter region, the collector region and the base region;   an array of deep trench islands within the deep-doped region, the deep trench islands conductively isolated from the buried layer and located between the collector region and the emitter region such that current between the connector region and the emitter region passes between the deep trench islands; and   the emitter region includes emitter contacts arranged as a plurality of linear arrays, each linear array separated from a nearest-neighbor linear array by a dielectric isolation structure.   
     
     
         31 . The device of  claim 30 , wherein the linear arrays are aligned along a direction of current between the emitter region and the collector region. 
     
     
         32 . The device of  claim 30 , further wherein the linear arrays of emitter contacts are arranged such that current between each linear array and the collector region follows a direct path between corresponding pairs of nearest-neighbor deep trench islands. 
     
     
         33 . A method of forming an electronic device, comprising:
 forming an emitter region, a collector region and a base region within a semiconductor substrate having a first conductivity type;   forming a deep-doped region having a second opposite conductivity type within the substrate, the deep-doped region extending to a buried layer having the second conductivity type that extends under the emitter region, the collector region and the base region; and   forming an array of deep trench islands within the deep-doped region, the deep trench islands conductively isolated from the buried layer and located between the collector region and the emitter region such that current between the connector region and the emitter region passes between the deep trench islands,   wherein the collector region includes collector contacts arranged as a plurality of linear arrays, each linear array separated from a nearest-neighbor linear array by a dielectric isolation structure.   
     
     
         34 . The method of  claim 33 , wherein the linear arrays are aligned along a direction of current between the emitter region and the collector region. 
     
     
         35 . The method of  claim 33 , further wherein the linear arrays of collector contacts are arranged such that current between each linear array and the emitter region follows a direct path between corresponding pairs of nearest-neighbor deep trench islands. 
     
     
         36 . The method of  claim 33 , wherein the deep trench islands each include a polysilicon core that conductively connects to the semiconductor substrate below the buried layer. 
     
     
         37 . The method of  claim 33 , wherein the emitter includes a doped region of the second conductivity type located within a well region of the first conductivity type. 
     
     
         38 . The method of  claim 33 , wherein the base region includes a well region of the first conductivity type that surrounds a well region of the second conductivity type. 
     
     
         39 . The method of  claim 33 , wherein the collector region includes a well region of the first second conductivity type surrounded by a well region of the second conductivity type. 
     
     
         40 . The method of  claim 33 , wherein the deep trench islands each include a conductive core laterally surrounded by an insulting liner. 
     
     
         41 . The method of  claim 33 , wherein the first conductivity type is P-type and the second conductivity type is N-type. 
     
     
         42 . An electronic device, comprising:
 an emitter region, a collector region and a base region formed within a semiconductor substrate having a first conductivity type;   a deep-doped region having a second opposite conductivity type, the deep-doped region extending to a buried layer having the second conductivity type that extends under the emitter region, the collector region and the base region;   an array of deep trench islands within the deep-doped region, the deep trench islands conductively isolated from the buried layer and located between the collector region and the emitter region such that current between the connector region and the emitter region passes between the deep trench islands.