Semiconductor device, display module, and electronic device

Abstract

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 n-th circuits (n is a natural number greater than or equal to 1); and   an n+1-th circuit,   wherein one of the n-th circuits comprises first to fifth transistors,   wherein the n+1-th circuit comprises sixth to tenth transistors,   wherein one of a source and a drain of the first transistor is electrically connected to a first line.   wherein the other of the source and the drain of the first transistor is electrically connected to a second gate line.   wherein one of a source and a drain of the second transistor is electrically connected to a second line.   wherein the other of the source and the drain of the second transistor is electrically connected to the second gate line,   wherein one of a source and a drain of the third transistor is electrically connected to a first gate line,   wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,   wherein a gate of the third transistor is electrically connected to the first gate line,   wherein one of a source and a drain of the fourth transistor is electrically connected to a third gate line.   wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,   wherein a gate of the fourth transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the fifth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,   wherein a gate of the fifth transistor is electrically connected to a third line,   wherein one of a source and a drain of the sixth transistor is electrically connected to a fourth line,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the seventh transistor is electrically connected to the second line,   wherein the other of the source and the drain of the seventh transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the eighth transistor is electrically connected to the second gate line,   wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the sixth transistor,   wherein a gate of the eighth transistor is electrically connected to the second gate line,   wherein one of a source and a drain of the ninth transistor is electrically connected to a fourth gate line,   wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the ninth transistor is electrically connected to the fourth gate line,   wherein one of a source and a drain of the tenth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the tenth transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the tenth transistor is electrically connected to a fifth line,   wherein the first and third lines are not connected to the n+1-th circuit,   wherein the fourth and fifth lines are not connected to the one of the n-th circuits,   wherein, in a period in which a signal input to the first line is low, a signal input to the third line has a period in which a signal is low,   wherein, in a period in which a signal input to the fourth line is low, a signal input to the fifth line has a period in which a signal is low,   wherein, in the first transistor, an area where the other of the source and the drain overlaps the gate is greater than the area where the one of the source and the drain overlaps the gate, and   wherein, in the sixth transistor, an area where the other of the source and the drain overlaps the gate is greater than the area where the one of the source and the drain overlaps the gate.   
     
     
         2 . A semiconductor device comprising:
 n-th circuits (n is a natural number greater than or equal to 1); and   an n+1-th circuit,   wherein one of the n-th circuits comprises first to fifth transistors,   wherein the n+1-th circuit comprises sixth to tenth transistors,   wherein one of a source and a drain of the first transistor is electrically connected to a first line to which a first clock signal is input.   wherein the other of the source and the drain of the first transistor is electrically connected to a second gate line.   wherein one of a source and a drain of the second transistor is electrically connected to a second line.   wherein the other of the source and the drain of the second transistor is electrically connected to the second gate line,   wherein one of a source and a drain of the third transistor is electrically connected to a first gate line,   wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,   wherein a gate of the third transistor is electrically connected to the first gate line,   wherein one of a source and a drain of the fourth transistor is electrically connected to a third gate line.   wherein the other of the source and the drain of the fourth transistor electrically connected to the gate of the first transistor,   wherein a gate of the fourth transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the fifth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,   wherein a gate of the fifth transistor is electrically connected to a third line to which a second clock signal is input,   wherein one of a source and a drain of the sixth transistor is electrically connected to a fourth line to which a third clock signal is input,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the seventh transistor is electrically connected to the second line,   wherein the other of the source and the drain of the seventh transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the eighth transistor is electrically connected to the second gate line,   wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the sixth transistor,   wherein a gate of the eighth transistor is electrically connected to the second gate line,   wherein one of a source and a drain of the ninth transistor is electrically connected to a fourth gate line,   wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the ninth transistor is electrically connected to the fourth gate line,   wherein one of a source and a drain of the tenth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the tenth transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the tenth transistor is electrically connected to a fifth line to which a fourth clock signal is input,   wherein the first and third lines are not connected to the n+1-th circuit,   wherein the fourth and fifth lines are not connected to the one of the n-th circuits,   wherein, in a period in which a signal input to the first line is low, a signal input to the third line has a period in which a signal is low,   wherein, in a period in which a signal input to the fourth line is low, a signal input to the fifth line has a period in which a signal is low,   wherein, in the first transistor, an area where the other of the source and the drain overlaps the gate is greater than the area where the one of the source and the drain overlaps the gate, and
 wherein, in the sixth transistor, an area where the other of the source and the drain overlaps the gate is greater than the area where the one of the source and the drain overlaps the gate. 
   
     
     
         3 . A semiconductor device comprising:
 n-th circuits (n is a natural number greater than or equal to 1); and   an n+1-th circuit,   wherein one of the n-th circuits comprises first to fifth transistors,   wherein the n+1-th circuit comprises sixth to tenth transistors,   wherein one of a source and a drain of the first transistor is electrically connected to a first line.   wherein the other of the source and the drain of the first transistor is electrically connected to a second gate line.   wherein one of a source and a drain of the second transistor is electrically connected to a second line.   wherein the other of the source and the drain of the second transistor is electrically connected to the second gate line,   wherein one of a source and a drain of the third transistor is electrically connected to a first gate line,   wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,   wherein a gate of the third transistor is electrically connected to the first gate line,   wherein one of a source and a drain of the fourth transistor is electrically connected to a third gate line.   wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,   wherein a gate of the fourth transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the fifth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,   wherein a gate of the fifth transistor is electrically connected to a third line,   wherein one of a source and a drain of the sixth transistor is electrically connected to a fourth line,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the seventh transistor is electrically connected to the second line,   wherein the other of the source and the drain of the seventh transistor is electrically connected to the third gate line,   wherein one of a source and a drain of the eighth transistor is electrically connected to the second gate line,   wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the sixth transistor,   wherein a gate of the eighth transistor is electrically connected to the second gate line,   wherein one of a source and a drain of the ninth transistor is electrically connected to a fourth gate line,   wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the ninth transistor is electrically connected to the fourth gate line,   wherein one of a source and a drain of the tenth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the tenth transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the tenth transistor is electrically connected to a fifth line,   wherein the first and third lines are not connected to the n+1-th circuit,   wherein the fourth and fifth lines are not connected to the one of the n-th circuits,   wherein, in a period in which a signal input to the first line is low, a signal input to the third line has a period in which a signal is low,   wherein, in a period in which a signal input to the fourth line is low, a signal input to the fifth line has a period in which a signal is low,   wherein a W/L (W is the channel width and L is the channel length) of the third transistor is 0.8 times or more and 1.2 times or less the W/L of the fourth transistor,   wherein the W/L of the eighth transistor is 0.8 times or more and 1.2 times or less the W/L of the of the ninth transistor,   wherein, in the first transistor, an area where the other of the source and the drain overlaps the gate is greater than the area where the one of the source and the drain overlaps the gate, and
 wherein, in the sixth transistor, an area where the other of the source and the drain overlaps the gate is greater than the area where the one of the source and the drain overlaps the gate. 
   
     
     
         4 . The semiconductor device according to  claim 2 ,
 wherein a W/L (W is the channel width and L is the channel length) of the third transistor is 0.8 times or more and 1.2 times or less the W/L of the fourth transistor, and
 wherein the W/L of the eighth transistor is 0.8 times or more and 1.2 times or less the W/L of the of the ninth transistor.