Integrated circuit and method of forming an integrated circuit

Abstract

An integrated circuit includes a first region. The integrated circuit further includes a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first region or the second region, wherein the power structure includes a second conductive structure overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a first region;   a first conductive structure in the first region, wherein the first conductive structure extends in a first direction;   a second region adjacent to the first region; and   a power structure configured to supply a voltage to the first region or the second region, wherein the power structure comprises a second conductive structure overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction.   
     
     
         2 . The integrated circuit of  claim 1 , further comprising a third conductive structure over the second conductive structure. 
     
     
         3 . The integrated circuit of  claim 2 , wherein the third conductive structure is in the first region. 
     
     
         4 . The integrated circuit of  claim 2 , wherein the third conductive structure is in the second region. 
     
     
         5 . The integrated circuit of  claim 2 , further comprising a conductive via electrically connecting the second conductive feature and the third conductive feature. 
     
     
         6 . The integrated circuit of  claim 1 , further comprising a third conductive structure parallel to the second conductive structure. 
     
     
         7 . The integrated circuit of  claim 6 , wherein a width of the third conductive structure in the second direction is equal to a width of the second conductive structure in the second direction. 
     
     
         8 . The integrated circuit of  claim 6 , wherein a width of the third conductive structure in the second direction is different from a width of the second conductive structure in the second direction. 
     
     
         9 . The integrated circuit of  claim 6 , wherein a length of the third conductive structure in the first direction is equal to a length of the second conductive structure in the first direction. 
     
     
         10 . The integrated circuit of  claim 9 , wherein an end of the third conductive structure is aligned with an end of the second conductive structure in the first direction. 
     
     
         11 . The integrated circuit of  claim 9 , wherein an end of the third conductive structure is offset in the first direction with respect to an end of the second conductive structure. 
     
     
         12 . The integrated circuit of  claim 6 , wherein a length of the third conductive structure in the first direction is different from a length of the second conductive structure in the first direction. 
     
     
         13 . A method of forming an integrated circuit, the method comprising:
 reducing a size of a conductive feature layout pattern of a cell layout, wherein the cell layout comprises a of conductive feature layout pattern;   placing a power layout pattern at least partially within the cell layout; and   extending a dimension of the conductive feature layout pattern in a direction toward a boundary of the power layout pattern, wherein the extending comprises increasing a dimension of the conductive feature layout pattern.   
     
     
         14 . The method of  claim 13 , wherein extending the dimension of the conductive feature comprises maintaining a minimum spacing requirement between the conductive feature layout pattern and a second conductive feature in the power layout pattern. 
     
     
         15 . The method of  claim 13 , wherein placing the power layout pattern comprises placing the power layout pattern extending across a boundary between a first region of the integrated circuit and a second region of the integrated circuit. 
     
     
         16 . The method of  claim 13  wherein placing the power layout pattern comprises placing the power layout pattern separated from all via layout patterns of the integrated circuit. 
     
     
         17 . An integrated circuit comprising:
 a first region;   a first conductive structure in the first region, wherein the first conductive structure extends in a first direction;   a second region adjacent to the first region; and   a power structure configured to supply a voltage to the first region or the second region, wherein the power structure comprises:
 a plurality of second conductive structures overlapping a boundary between the first region and the second region, wherein the first conductive structure is separated from each of the plurality of second conductive structures in the first direction; and 
   a third conductive structure electrically connected to each of the plurality of second conductive structures.   
     
     
         18 . The integrated circuit of  claim 17 , wherein a width of a first conductive structure of the plurality of second conductive structures in the second direction is different from a width of a second conductive structure of the plurality of second conductive structures in the second direction. 
     
     
         19 . The integrated circuit of  claim 17 , wherein an end of a first conductive structure of the plurality of second conductive structures is offset with respect to an end of a second conductive structure of the plurality of second conductive structures in the first direction. 
     
     
         20 . The integrated circuit of  claim 17 , wherein a length of a first conductive structure of the plurality of second conductive structures in the first direction is different from a length of a second conductive structure of the plurality of second conductive structures in the first direction.