High-speed linear charge pump circuits for clock data recovery

Abstract

The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.

What is claimed is: 
     
         1 . A communication system comprising:
 a variable gain amplifier (VGA) configured to generate an amplified data signal based on a received data signal;   a first sampler configured to generate a first data signal based on the amplified data signal;   a second sampler configured to generate a second data signal based on the amplified data signal;   a phase detector configured to generate an early signal and a late signal using at the first data signal and the second data signal; and
 a charge pump circuit comprising a bias section and a switch section, the bias section being configured to generate a first bias signal and a second bias signal, the switch section being configured for generating a charge current, the switch section comprises a first switch coupled to the early signal and a first resistor directly coupled to the first switch, the switch section further comprising a second switch coupled to the late signal and a second resistor directly coupled to the second switch. 
   
     
     
         2 . The communication system of  claim 1  wherein the charge pump circuit further comprises a digital-to-analog converter (DAC) for providing a control current to the bias section, wherein the bias section is configured to control magnitudes of the first and second bias signal according to the control current. 
     
     
         3 . The communication system of  claim 1  wherein the charge pump circuit further comprises a loop-filter resistor and a first capacitor, the loop-filter resistor being coupled to the first resistor. 
     
     
         4 . The communication system of  claim 1  wherein the first switch comprises a PMOS transistor, a gate of the PMOS transistor is coupled to the early signal. 
     
     
         5 . The communication system of  claim 4  wherein a drain of the PMOS transistor is coupled to the first resistor. 
     
     
         6 . The communication system of  claim 1  further comprising a voltage controlled oscillator coupled to the charge pump circuit. 
     
     
         7 . The communication system of  claim 1  wherein the switch section further comprises a third switch having a first terminal coupled to an inverse early signal and having a second terminal directly coupled to the first resistor. 
     
     
         8 . The communication system of  claim 1  wherein the bias section comprises an operational amplifier coupled to a voltage source. 
     
     
         9 . The communication system of  claim 1  wherein the first sampler comprises a data sampler, and the second sampler comprises an edge sampler. 
     
     
         10 . The communication system of  claim 1  further comprising a clock data recovery circuit, the clock data recovery circuit comprising the phase detector and the charge pump circuit. 
     
     
         11 . A clock data recovery (CDR) circuit comprising:
 a phase detector configured to generate an early signal and a late signal using at least a first sample signal and a second sample signal;   a voltage controlled oscillator configured got generate a clock signal based on a control voltage; and   a charge pump circuit configured to generate the control voltage using at least the early signal and the late signal, the charge pump circuit comprising:
 a bias section configured to generate a first bias signal and a second bias signal; 
 a loop filter; and 
   a switch section configured for generating a charge current, the switch section comprises a first switch coupled to the early signal and a first resistor directly coupled to the first switch, the switch section further comprising a second switch coupled to the late signal and a second resistor directly coupled to the second switch.   
     
     
         12 . The CDR circuit of  claim 11  comprising a data sampler for generating the first sample signal and an edge sampler for generating the second sample signal. 
     
     
         13 . The CDR circuit of  claim 12  wherein the data sampler and the edge sampler are coupled to the voltage control oscillator. 
     
     
         14 . The CDR circuit of  claim 11  wherein the first sample signal comprises in-phase data and the second sample signal comprises quadrature signal. 
     
     
         15 . The CDR circuit of  claim 11  wherein the switch section further comprises a third switch coupled to an inverse early signal. 
     
     
         16 . The charge pump circuit of  claim 11  further comprising a capacitance coupled to a drain terminal of the first switch. 
     
     
         17 . A serializer/deserializer system comprising:
 a communication interface for receiving data signal;   a variable gain amplifier (VGA) configured to generate an amplified data signal based on the data signal;   a first sampler configured to generate an in-phase signal based on the amplified data signal;   a second sampler configured to generate a quadrature signal based on the amplified data signal;   a phase detector configured to generate an early signal and a late signal using at the in-phase signal and the quadrature signal;   a charge pump circuit configured to generate a control voltage and comprising a bias section and a switch section, the switch section comprises a first switch coupled to the early signal and a first resistor directly coupled to the first switch, the switch section further comprising a second switch coupled to the late signal and a second resistor directly coupled to the second switch; and   a voltage controlled oscillator configured to generate a clock signal based on the control voltage.   
     
     
         18 . The serializer/deserializer system of  claim 17  wherein the first sampler and the second sampler are coupled to the voltage controlled oscillator. 
     
     
         19 . The serializer/deserializer system of  claim 17  further comprising a loop filter coupled to the charge pump circuit. 
     
     
         20 . The serializer/deserializer system of  claim 17  further comprising a loop filter coupled to the bias section, the bias section being configured to generate bias signals.