Field-effect transistor with size-reduced source/drain epitaxy and fabrication method thereof

Abstract

Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

What is claimed is: 
     
         1 . A fin field-effect transistor comprising:
 a substrate;   a channel formed in a predetermined region of the substrate;   a gate formed in a predetermined region of the channel;   source/drain regions formed at both sides of the channel along side surfaces of the channel on the substrate; and   an insulating layer formed between the gate and the source/drain regions on an upper portion of the channel, so as to wrap the channel,   wherein a maximum width ratio (W 1 /W 2 ) of a width W 2  of each of the source/drain regions to a width W 1  of the channel is 1 based on a width direction (Y-axis direction, width) of the channel.   
     
     
         2 . The fin field-effect transistor of  claim 1 , wherein the insulating layer includes one or more insulating materials selected from the group consisting of SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Si 3 N 4 , perovskite oxide, and a combination thereof. 
     
     
         3 . The fin field-effect transistor of  claim 1 , wherein the substrate includes silicon, germanium, tin, compounds of Group III to Group V, and a hetero-combined material. 
     
     
         4 . The fin field-effect transistor of  claim 1 , wherein the substrate is doped with one or more n-type doping materials selected from among P, As, and Sb or one or more p-type doping materials selected from among B, BF 2 , Al, and Ga. 
     
     
         5 . The fin field-effect transistor of  claim 1 , wherein the gate is a polysilicon gate or a replacement metal gate. 
     
     
         6 . The fin field-effect transistor of  claim 1 , wherein a metal silicide layer is formed on upper portions of the source/drain regions so as to wrap the upper portions of the source/drain regions. 
     
     
         7 . The fin field-effect transistor of  claim 1 , wherein the field-effect transistor has any one among a multi-gate structure including a double- or triple-gate FinFET, a GAA (gate-all-around) structure (nanowire, nanosheet), a lateral structure in which channels are arranged in a lateral direction, or a vertical structure in which the channels are arranged in a vertical direction. 
     
     
         8 . A method of manufacturing a fin field-effect transistor, comprising:
 (a) forming a channel, a gate, and an insulating layer in a predetermined region of a substrate so that the insulating layer is formed from both sides of the gate on an upper portion of the substrate;   (b) performing etching along side surfaces of the channel and the insulating layer so as to etch even an upper portion of one side of the substrate through an etching process for forming source/drain regions, so that a designated region of the substrate and a region of the channel are exposed, and so that the insulating layer, patterned so as to wrap the exposed region of the substrate, is formed on the substrate; and   (c) forming the source/drain regions, in which lateral growth of an epitaxial structure in a Y-axis direction is restricted through a selective epitaxial growth process, in the exposed region of the substrate and the channel,   wherein the fin field-effect transistor is manufactured so that a maximum width ratio (W 1 /W 2 ) of a width W 2  of each of the source/drain regions to a width W 1  of the channel is 1 based on a width direction (Y-axis direction, width) of the channel.   
     
     
         9 . The method of  claim 8 , wherein the etching process of step (b) includes simultaneously forming the insulating layer, which is in contact with a side surface of the gate, and the patterned insulating layer, which is positioned on the substrate, using one mask. 
     
     
         10 . The method of  claim 8 , wherein the etching process of step (b) is performed as an anisotropic etching process. 
     
     
         11 . The method of  claim 8 , further comprising:
 after the forming the source/drain regions in step (c),   forming a replacement metal gate and then removing the patterned insulating layer on the substrate; and   forming a metal silicide layer.   
     
     
         12 . The method of  claim 8 , wherein a punch-through stopper process is further performed prior to the selective epitaxial growth process in step (c).