Memory device

Abstract

According to one embodiment, a memory device includes a memory cell and a first select transistor. The memory cell includes: a variable resistance memory region; a first semiconductor layer being in contact with the variable resistance memory region; a first insulating layer being in contact with the first semiconductor layer; and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes: a second semiconductor layer; a second insulating layer being in contact with the second semiconductor layer; and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.

What is claimed is: 
     
         1 . A memory device, comprising:
 a plurality of memory cells each including:
 a variable resistance memory region extending in a first direction that is orthogonal to a semiconductor substrate; 
 a first semiconductor layer extending in the first direction and being in contact with the variable resistance memory region; 
 a first insulating layer extending in the first direction and being in contact with the first semiconductor layer; and 
 a first voltage application electrode extending in a second direction that is orthogonal to the first direction and being in contact with the first insulating layer; 
   a first select transistor including:
 a second semiconductor layer extending in the first direction; 
 a second insulating layer extending in the first direction and being in contact with the second semiconductor layer; and 
 a second voltage application electrode extending in the second direction and being in contact with the second insulating layer; and 
   a memory cell string including the first select transistor, the memory cells, and a third voltage application electrode, the memory cells being coupled in series in the first direction, one end of the first select transistor being coupled to one end of one of the memory cells that is provided at a first end portion, the third voltage application electrode being coupled to one end of one of the memory cells that is provided at a second end portion.   
     
     
         2 . The memory device according to  claim 1 , wherein
 the third voltage application electrode is commonly coupled to the memory cell strings that are adjacent to each other in a third direction that is orthogonal to the first and second directions.   
     
     
         3 . The memory device according to  claim 1 , wherein
 the variable resistance memory region is a phase-change element, and contains at least one of: GeTe and Sb 2 Te 3 ; GeTe and BiSbTe; or Ge, Sb, and Te or a chalcogenide material.   
     
     
         4 . The memory device according to  claim 1 , wherein
 the variable resistance memory region contains at least one of TiO x , WO x , HfO x , or TaO x .   
     
     
         5 . The memory device according to  claim 1 , further comprising:
 a plurality of fifth voltage application electrodes each coupled to another end of the first select transistor, and extending in a third direction that is orthogonal to the first and second directions; and   a sequencer configured to selectively perform a read operation or a write operation by applying a voltage between at least one of the fifth voltage application electrodes and the third voltage application electrode.   
     
     
         6 . The memory device according to  claim 1 , wherein
 silicon nitride is provided inside the variable resistance memory region.   
     
     
         7 . The memory device according to  claim 1 , wherein
 an air layer is provided inside the variable resistance memory region.   
     
     
         8 . The memory device according to  claim 1 , wherein
 a core oxide film layer is provided inside the variable resistance memory region.   
     
     
         9 . A memory device comprising:
 a plurality of memory cells each including:
 a variable resistance memory region extending in a first direction that is orthogonal to a semiconductor substrate; 
 a first semiconductor layer extending in the first direction and being in contact with the variable resistance memory region; 
 a first insulating layer extending in the first direction and being in contact with the first semiconductor layer; and 
 a first voltage application electrode extending in a second direction that is orthogonal to the first direction and being in contact with the first insulating layer; 
   a first select transistor including:
 a second semiconductor layer extending in the first direction; 
 a second insulating layer extending in the first direction and being in contact with the second semiconductor layer; and 
 a second voltage application electrode extending in the second direction and being in contact with the second insulating layer; 
   a second select transistor including:
 a third semiconductor layer extending in the first direction; 
 a third insulating layer extending in the first direction and being in contact with the third semiconductor layer; and 
 a fourth voltage application electrode extending in the second direction and being in contact with the third insulating layer; and 
   a memory cell string including the first and second select transistors, the memory cells, and a third voltage application electrode, the memory cells being coupled in series in the first direction, one end of the first select transistor being coupled to one end of one of the memory cells that is provided at a first end portion, one end of the second select transistor being coupled to one end of one of the memory cells that is provided at a second end portion, the third voltage application electrode being coupled to another end of the second select transistor.   
     
     
         10 . The memory device according to  claim 9 , wherein
 the third voltage application electrode is commonly coupled to the memory cell strings which are adjacent to each other in a third direction that is orthogonal to the first and second directions.   
     
     
         11 . The memory device according to  claim 9 , wherein
 the variable resistance memory region is a phase-change element, and contains at least one of: GeTe and Sb 2 Te 3 ; GeTe and BiSbTe; or Ge, Sb, and Te or a chalcogenide material.   
     
     
         12 . The memory device according to  claim 9 , wherein
 the variable resistance memory region contains at least one of TiO x , WO x , HfO x , or TaO x .   
     
     
         13 . The memory device according to  claim 9 , further comprising:
 a plurality of fifth voltage application electrodes each coupled to another end of the first select transistor, and extending in a third direction that is orthogonal to the first and second directions; and   a sequencer configured to selectively perform a read operation or a write operation by applying a voltage between at least one of the fifth voltage application electrodes and the third voltage application electrode.   
     
     
         14 . The memory device according to  claim 9 , wherein
 silicon nitride is provided inside the variable resistance memory region.   
     
     
         15 . The memory device according to  claim 9 , wherein
 an air layer is provided inside the variable resistance memory region.   
     
     
         16 . A memory device comprising:
 a plurality of memory cell each including:
 a variable resistance memory region extending in a first direction that is orthogonal to a semiconductor substrate and being in a columnar or cylindrical shape; 
 a first semiconductor layer extending in the first direction and covering an outer periphery of the variable resistance memory region; 
 a first insulating layer extending in the first direction and covering an outer periphery of the first semiconductor layer; and 
 a first voltage application electrode extending in a second direction that is orthogonal to the first direction and covering a part of an outer periphery of the first insulating layer; 
   a first select transistor including:
 a second semiconductor layer extending in the first direction and being in a columnar or cylindrical shape; 
 a second insulating layer extending in the first direction and covering an outer periphery of the second semiconductor layer; and 
 a second voltage application electrode extending in the second direction and covering an outer periphery of the second insulating layer; and 
   a memory cell string including the first select transistor, the memory cells, and a third voltage application electrode, the memory cells being coupled in series in the first direction, one end of the first select transistor being coupled to one end of one of the memory cells that is provided at a first end portion, the third voltage application electrode being coupled to one end of one of the memory cells that is provided at a second end portion.   
     
     
         17 . The memory device according to  claim 16 , further comprising:
 the second select transistor including:
 a third semiconductor layer extending in the first direction and being in a columnar or cylindrical shape; 
 a third insulating layer extending in the first direction and covering an outer periphery of the third semiconductor layer; and 
 a fourth voltage application electrode extending in the second direction and covering an outer periphery of the third insulating layer, 
   wherein   the third voltage application electrode is coupled to the one end of the memory cell that is provided at the second end portion via the second select transistor.   
     
     
         18 . The memory device according to  claim 16 , further comprising:
 a plurality of fifth voltage application electrodes each coupled to another end of the first select transistor, and extending in a third direction that is orthogonal to the first and second directions; and   a sequencer configured to selectively perform a read operation or a write operation by applying a voltage between at least one of the fifth voltage application electrodes and the third voltage application electrode.   
     
     
         19 . A memory device comprising:
 a memory pillar including:
 first voltage application electrodes and first insulating layers alternately stacked in a first direction that is orthogonal to a semiconductor substrate; 
 a cylindrical first hole that penetrates the first voltage application electrodes and the first insulating layers in the first direction; 
 a cylindrical second insulating layer covering an inner wall of the first hole and extending in the first direction; 
 a cylindrical first semiconductor layer covering an inner wall of the second insulating layer and extending in the first direction; and 
 a cylindrical or columnar-shaped variable resistance memory region covering an inner wall of the first semiconductor layer and extending in the first direction; 
   a first select transistor including:
 a cylindrical second hole that penetrates a second voltage application electrode and communicates with the first hole, the second voltage application electrode being provided on the first voltage application electrodes and the first insulating layers in the first direction; 
 a cylindrical third insulating layer covering an inner wall of the second hole and extending in the first direction; and 
 a cylindrical third semiconductor layer covering an inner wall of the third insulating layer and extending in the first direction; and 
   a memory cell string including the first select transistor, the memory pillar, and a third voltage application electrode, one end of the first select transistor being coupled to a first end of the memory pillar, the third voltage application electrode being coupled to a second end of the memory pillar.   
     
     
         20 . The memory device according to  claim 19 , further comprising:
 a fifth voltage application electrode coupled to another end of the first select transistor, and extending in a third direction that is orthogonal to the first direction and a second direction; and   a sequencer configured to selectively perform a read operation or a write operation by applying a voltage between at least one of the fifth voltage application electrodes and the third voltage application electrode.