Display controller to prevent visual artifacts with spread spectrum clocking

Abstract

A display controller and method for performing the same operations are described. In on embodiment, the display controller comprises a spread spectrum clock (SSC) modulator having a first input coupled to receive a non-SSC modulated clock and operable to generate a SSC modulated clock in response to the non-SSC modulated clock, a video data transfer portion coupled to receive the SSC modulated clock and operable to output data for display in response to the SSC modulated clock, and a second portion coupled to receive the non-SSC modulated clock.

1 . (canceled) 
     
     
         2 . A display controller comprising:
 a clock generator to generate a modulated clock based on a base clock;   first logic circuitry to be clocked by the modulated clock, the first logic circuitry including a first counter to be clocked by the modulated clock, the first logic circuitry to output an enable signal based on the first counter, the enable signal associated with transfer of video data to a display; and   second logic circuitry to be clocked by the base clock, the second logic circuitry including a second counter to be clocked by the base clock, the second logic circuitry to output a synchronization signal based on the second counter, the synchronization signal to define a horizontal line access cycle, the second logic circuitry to reset the first counter and the second counter based on the base clock.   
     
     
         3 . The display controller of  claim 2 , wherein the modulated clock is a spread spectrum clock, and the base clock is unmodulated. 
     
     
         4 . The display controller of  claim 2 , wherein the synchronization signal is a first synchronization signal and the second logic circuitry is to output a second synchronization signal based on the first synchronization signal, the second synchronization signal to define a vertical frame access cycle. 
     
     
         5 . The display controller of  claim 4 , wherein the second logic circuitry includes a third counter to be clocked by the first synchronization signal, and the second logic circuitry is to generate the second synchronization signal based on the third counter. 
     
     
         6 . The display controller of  claim 5 , wherein the second logic circuitry is to reset the third counter based on the base clock. 
     
     
         7 . The display controller of  claim 6 , wherein the second logic circuitry is to:
 generate a first reset signal to reset the first counter and the second counter; and   generated a second reset signal to reset the third counter, the second reset signal different from the first reset signal.   
     
     
         8 . The display controller of  claim 2 , wherein the clock generator is to generate the modulated clock based on the base clock and a reference clock different from the base clock. 
     
     
         9 . A system comprising:
 a display;   memory to store video data;   first logic circuitry to be clocked by a modulated clock, the first logic circuitry including a first counter to be clocked by the modulated clock, the first logic circuitry to output an enable signal based on the first counter, the enable signal associated with transfer of the video data to the display; and   second logic circuitry to be clocked by a base clock used to generate the modulated clock, the second logic circuitry including a second counter to be clocked by the base clock, the second logic circuitry to output a synchronization signal based on the second counter, the synchronization signal to define a horizontal line access cycle, the second logic circuitry to reset the first counter and the second counter based on the base clock.   
     
     
         10 . The system of  claim 9 , wherein the modulated clock is a spread spectrum clock, and the base clock is unmodulated. 
     
     
         11 . The system of  claim 9 , wherein the synchronization signal is a first synchronization signal and the second logic circuitry is to output a second synchronization signal based on the first synchronization signal, the second synchronization signal to define a vertical frame access cycle. 
     
     
         12 . The system of  claim 11 , wherein the second logic circuitry includes a third counter to be clocked by the first synchronization signal, and the second logic circuitry is to generate the second synchronization signal based on the third counter. 
     
     
         13 . The system of  claim 12 , wherein the second logic circuitry is to reset the third counter based on the base clock. 
     
     
         14 . The system of  claim 13 , wherein the second logic circuitry is to:
 generate a first reset signal to reset the first counter and the second counter; and   generated a second reset signal to reset the third counter, the second reset signal different from the first reset signal.   
     
     
         15 . The system of  claim 9 , further including a clock generator to generate the modulated clock based on the base clock and a reference clock different from the base clock. 
     
     
         16 . A method comprising:
 modulating a base clock to generate a modulated clock;   generating, with first logic circuitry clocked with the modulated clock, an enable signal associated with transfer of video data to a display, the enable signal generated based on a first counter included in the first logic circuitry, the first counter clocked with the modulated clock;   generating, with second logic circuitry clocked with the base clock, a synchronization signal to define a horizontal line access cycle, the synchronization signal generated based on a second counter included in the second logic circuitry, the second counter clocked with the base clock; and   resetting the first counter and the second counter based on the base clock.   
     
     
         17 . The method of  claim 16 , wherein the modulated clock is a spread spectrum clock, and the base clock is unmodulated. 
     
     
         18 . The method of  claim 16 , wherein the synchronization signal is a first synchronization signal, and further including generating, with the second logic circuitry, a second synchronization signal based on the first synchronization signal, the second synchronization signal to define a vertical frame access cycle. 
     
     
         19 . The method of  claim 18 , wherein the generating of the second synchronization signal includes generating the second synchronization signal based on a third counter included in the second logic circuitry, the third counter clocked with the first synchronization signal. 
     
     
         20 . The method of  claim 19 , further including resetting the third counter based on the base clock. 
     
     
         21 . The method of  claim 20 , wherein the resetting of the first counter and the second counter includes generating a first reset signal to reset the first counter and the second counter, and the resetting of the third counter generating a second reset signal to reset the third counter.