Semiconductor device and operating method of the semiconductor device

Abstract

A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.

What is claimed is: 
     
         1 . A method of operating a semiconductor device comprising memory strings that are coupled between a common source line and a bit line, wherein each of the memory strings comprises memory cells and select transistors, the method comprising:
 applying a first pass voltage to unselected word lines among word lines coupled to the memory cells, respectively;   precharging at least one of the common source line and the bit line when the first pass voltage is applied;   increasing the first pass voltage to a second pass voltage; and   sensing data from a selected memory cell of a selected memory string among the memory strings.   
     
     
         2 . The method of  claim 1 , wherein the each of the memory strings comprises a dummy memory cell coupled between the memory cells and the select transistors, and
 wherein the first pass voltage is applied to a dummy word line that is coupled to the dummy memory cell when the first pass voltage is applied to the unselected word lines.   
     
     
         3 . The method of  claim 1 , wherein select lines are coupled to the select transistors, respectively, when the bit line is precharged, a turn-on voltage is applied to a drain select line among the select lines and a turn-off voltage is applied to a source select line among the select lines, when the first pass voltage is applied. 
     
     
         4 . The method of  claim 1 , wherein select lines are coupled to the select transistors, respectively, when the bit line is precharged, a turn-on voltage is applied to a selected drain select line among the select lines and a turn-off voltage is applied to an unselected drain select line among the select lines, when the second pass voltage is applied. 
     
     
         5 . The method of  claim 1 , wherein select lines are coupled to the select transistors, respectively, when the common source line is precharged, a turn-on voltage is applied to a source select line among the select lines and a turn-off voltage is applied to a drain select line among the select lines, when the first pass voltage is applied. 
     
     
         6 . The method of  claim 1 , wherein select lines are coupled to the select transistors, respectively, when the common source line is precharged, a turn-on voltage is applied to a selected source select line among the select lines and a turn-off voltage is applied to an unselected source select line among the select lines, when the second pass voltage is applied. 
     
     
         7 . The method of  claim 1 , wherein the first pass voltage is applied to a selected word line among the word lines when the first pass voltage is applied to the unselected word lines, and
 wherein a read voltage is applied the selected word line after applying the second pass voltage to the selected word line.   
     
     
         8 . The method of  claim 7 , wherein a voltage of the selected word line is decreased from the second pass voltage to a ground voltage, and then increased to the read voltage. 
     
     
         9 . The method of  claim 1 , wherein introduction of a carrier from the common source line or the bit line into channel regions of the memory strings is mitigated when the first pass voltage is applied. 
     
     
         10 . A semiconductor device, comprising:
 memory strings coupled between a common source line and a bit line; and   a peripheral circuit coupled to the memory strings through a plurality of word lines, and configured to set biases to the word lines before performing a sensing operation,   wherein the peripheral circuit precharges at least one of the common source line and the bit line concurrently with applying a first pass voltage to the word lines before the peripheral circuit increases the first pass voltage to a second pass voltage to set the biases of the word lines.