Sinusoidal shaped capacitor architecture in oxide

Abstract

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a first metal layer;   an oxide layer on top of the first metal layer, the oxide layer comprising a first location that includes a plurality of trenches and a second location that does not include trenches; and   a combination of layers on the oxide layer at the first location, the combination of layers comprising a bottom metal layer, a dielectric layer, and a top metal layer;   wherein the second location has formed thereon the bottom metal layer of the combination of layers without the dielectric layer and the top metal layer.   
     
     
         22 . The semiconductor device as recited in  claim 21 , wherein top and bottom corners of the plurality of trenches are rounded. 
     
     
         23 . The semiconductor device as recited in  claim 21 , further comprising a first via at the second location creating contact with the bottom metal layer. 
     
     
         24 . The semiconductor device as recited in  claim 23 , wherein the combination of layers at the first location form a metal-insulator-metal (MIM) capacitor with an oscillating pattern. 
     
     
         25 . The semiconductor device as recited in  claim 24 , further comprising a second via at a location creating contact with the top metal layer. 
     
     
         26 . The semiconductor device as recited in  claim 25 , further comprising a second metal layer over the second via. 
     
     
         27 . A semiconductor device fabrication process comprising:
 forming a first metal layer;   forming an oxide layer on top of the first metal layer, the oxide layer comprising a first location that includes a plurality of trenches and a second location that does not include trenches; and   forming a combination of layers on the oxide layer at the first location, the combination of layers comprising a bottom metal layer, a dielectric layer, and a top metal layer;   wherein the second location has formed thereon the bottom metal layer of the combination of layers without the dielectric layer and the top metal layer.   
     
     
         28 . The semiconductor device fabrication process as recited in  claim 27 , wherein top and bottom corners of the plurality of trenches are rounded. 
     
     
         29 . The semiconductor device fabrication process as recited in  claim 27 , wherein a thickness of the oxide layer on top of the first metal layer is at least an order of magnitude greater than a thickness of a gate silicon dioxide layer formed for active devices. 
     
     
         30 . The semiconductor device fabrication process as recited in  claim 27 , wherein the process further comprises placing a first via at the second location creating contact with the bottom metal layer. 
     
     
         31 . The semiconductor device fabrication process as recited in  claim 27 , wherein the combination of layers at the first location form a metal-insulator-metal (MIM) capacitor with an oscillating pattern. 
     
     
         32 . The semiconductor device fabrication process as recited in  claim 31 , wherein the process further comprises placing a second via at a location creating contact with the top metal layer. 
     
     
         33 . The semiconductor device fabrication process as recited in  claim 32 , wherein the process further comprises placing a second metal layer over the second via. 
     
     
         34 . A method for fabricating a semiconductor device comprising:
 depositing an oxide layer on top of a first metal layer, the oxide layer having a first location and a second location;   forming a plurality of trenches in the oxide layer at the first location but not the second location;   depositing a bottom metal layer over the oxide layer;   depositing a dielectric layer on top of the bottom metal layer;   depositing a top metal layer on top of the dielectric layer; and   removing the top metal layer and the dielectric layer at the second location of the oxide layer.   
     
     
         35 . The method as recited in  claim 34 , further comprising rounding top and bottom corners of the plurality of trenches. 
     
     
         36 . The method as recited in  claim 34 , wherein a thickness of the oxide layer on top of the first metal layer is at least an order of magnitude greater than a thickness of a gate silicon dioxide layer formed for active devices. 
     
     
         37 . The method as recited in  claim 34 , further comprising placing a first via at the second location creating contact with the bottom metal layer. 
     
     
         38 . The method as recited in  claim 37 , wherein the bottom metal layer, dielectric layer, and top metal layer form a a metal-insulator-metal (MIM) capacitor with an oscillating pattern. 
     
     
         39 . The method as recited in  claim 38 , further comprising placing a second via at location creating contact with the top metal layer. 
     
     
         40 . The method as recited in  claim 39 , further comprising placing a second metal layer over the second via.