Overwrite read methods for memory devices

Abstract

A method is provided that includes applying a read voltage to a resistance-switching memory cell to determine a first memory cell resistance, applying a first write voltage to the resistance-switching memory cell, applying the read voltage to the resistance-switching memory cell to determine a second memory cell resistance, and comparing the first memory cell resistance to the second memory cell resistance to determine that the resistance-switching memory cell is in a first memory state or a second memory state.

1 . A method comprising:
 applying a read voltage to a resistance-switching memory cell to determine a first memory cell resistance;   applying a first write voltage to the resistance-switching memory cell;   applying the read voltage to the resistance-switching memory cell to determine a second memory cell resistance; and   comparing the first memory cell resistance to the second memory cell resistance to determine that the resistance-switching memory cell is in a first memory state or a second memory state.   
     
     
         2 . The method of  claim 1 , wherein the first write voltage does not switch a memory state of the resistance-switching memory cell. 
     
     
         3 . The method of  claim 1 , further comprising:
 determining that the first memory cell resistance is less than the second memory cell resistance;   applying a second write voltage to the resistance-switching memory cell; and   determining that the resistance-switching memory cell is in the first memory state.   
     
     
         4 . The method of  claim 3 , wherein:
 the first write voltage switches the resistance-switching memory cell from the first memory state to the second memory state; and   the second write voltage switches the resistance-switching memory cell from the second memory state to the first memory state.   
     
     
         5 . The method of  claim 3 , wherein the first write voltage has a polarity opposite the second write voltage. 
     
     
         6 . The method of  claim 1 , further comprising:
 determining that the first memory cell resistance is not less than the second memory cell resistance; and   determining that the resistance-switching memory cell is in the second memory state.   
     
     
         7 . The method of  claim 1 , further comprising:
 determining that the first memory cell resistance is greater than the second memory cell resistance;   applying a second write voltage to the resistance-switching memory cell; and   determining that the resistance-switching memory cell is in the second memory state.   
     
     
         8 . The method of  claim 7 , wherein:
 the first write voltage switches the resistance-switching memory cell from the second memory state to the first memory state; and   the second write voltage switches the resistance-switching memory cell from the first memory state to the second memory state.   
     
     
         9 . The method of  claim 7 , wherein the first write voltage has a polarity opposite the second write voltage. 
     
     
         10 . The method of  claim 1 , further comprising:
 determining that the first memory cell resistance is not greater than the second memory cell resistance; and   determining that the resistance-switching memory cell is in the first memory state.   
     
     
         11 . The method of  claim 1 , wherein the resistance-switching memory cell comprises any of a spin-transfer-torque driven magnetoresistive random access memory cell, a voltage control of magnetic anisotropy magnetoresistive random access memory cell, a spin orbit torque driven magnetoresistive random access memory cell, a phase change random access memory cell, and a reversible resistance-switching random access memory cell. 
     
     
         12 . A system comprising:
 a control circuit configured to:
 apply a read voltage to a resistance-switching memory cell to determine a first memory cell resistance; 
 apply a first write voltage to the resistance-switching memory cell; 
 determine a second memory cell resistance of the resistance-switching memory cell at the first write voltage; and 
 compare the first memory cell resistance to the second memory cell resistance to determine that the resistance-switching memory cell is in a first memory state or a second memory state. 
   
     
     
         13 . The system of  claim 12 , wherein the first write voltage does not switch a memory state of the resistance-switching memory cell. 
     
     
         14 . The system of  claim 12 , wherein the control circuit is further configured to:
 determine that the first memory cell resistance is less than the second memory cell resistance;   apply a second write voltage to the resistance-switching memory cell; and   determine that the resistance-switching memory cell is in the first memory state.   
     
     
         15 . The system of  claim 14 , wherein:
 the first write voltage switches the resistance-switching memory cell from the first memory state to the second memory state; and   the second write voltage switches the resistance-switching memory cell from the second memory state to the first memory state.   
     
     
         16 . The system of  claim 12 , wherein the control circuit is further configured to:
 determine that the first memory cell resistance is not less than the second memory cell resistance; and   determine that the resistance-switching memory cell is in the second memory state.   
     
     
         17 . The system of  claim 12 , wherein the control circuit is further configured to:
 determine that the first memory cell resistance is greater than the second memory cell resistance;   apply a second write voltage to the resistance-switching memory cell; and   determine that the resistance-switching memory cell is in the second memory state.   
     
     
         18 . The system of  claim 12 , wherein the resistance-switching memory cell comprises any of a magnetoresistive random access memory cell, a phase change memory cell and a reversible resistance-switching memory cell. 
     
     
         19 . A method comprising:
 measuring read currents of each of a plurality of resistance-switching memory cells;   comparing each of the measured read currents to a first reference current to determine a first set of bit values for each of the resistance-switching memory cells;   comparing each of the measured read currents to a second reference current to determine a second set of bit values for each of the resistance-switching memory cells;   comparing each of the measured read currents to a third reference current to determine a third set of bit values for each of the resistance-switching memory cells;   applying a write voltage to each of the resistance-switching memory cells;   comparing each of the measured read currents to the second reference current to determine a fourth set of bit values for each of the resistance-switching memory cells; and   performing logic operations on the first set of bit values, the second set of bit values, the third set of bit values and the fourth set of bit values to correct bit errors in the first set of bit values.   
     
     
         20 . The method of  claim 19 , wherein each of the wherein the resistance-switching memory cell comprises any of a spin-transfer-torque driven magnetoresistive random access memory cell, a voltage control of magnetic anisotropy magnetoresistive random access memory cell, a spin orbit torque driven magnetoresistive random access memory cell, a phase change random access memory cell, and a reversible resistance-switching random access memory cell.