High mobility strained channels for fin-based nmos transistors

Abstract

Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a source region;   a drain region;   a body at least partially between the source and drain regions;   a layer including germanium and over the body, wherein the body has a width between two portions of the layer, wherein the layer has a thickness, and wherein the width is at most 4 times the thickness; and   a gate structure at least above the body, the gate structure including a gate electrode and a gate dielectric.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the width is at most 2 times the thickness. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the width is 4 nm or less, and the thickness is 2 nm or less. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the body is a body of silicon and the layer is a layer of germanium. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the body includes tensile strain. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the body is part of a fin. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the body includes a nanowire or nanoribbon. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the body is a body of silicon that is part of a fin, and wherein the fin is configured with a <110> orientation. 
     
     
         9 . The integrated circuit of  claim 1 , wherein at least one of the source and drain regions comprise N+ doped semiconductor material. 
     
     
         10 . The integrated circuit of  claim 1 , wherein the layer comprises silicon and germanium, with the germanium concentration between 10 atomic % to 90 atomic % germanium. 
     
     
         11 . The integrated circuit of  claim 1 , wherein the layer is over at least part of two opposing sidewalls and at least part of top portion of the body. 
     
     
         12 . A computing system comprising the integrated circuit of  claim 1 . 
     
     
         13 . An integrated circuit, comprising:
 a body including silicon;   a gate structure adjacent to at least top and side walls of a portion of the body, the gate structure including a gate electrode and a gate dielectric;   a layer including germanium, the layer between at least the top of the portion of the body and the gate dielectric, the layer having a thickness, wherein the body has a horizontal width, and wherein a ratio of the width to the thickness is at most 4; and   a source region and a drain region, the portion of the body at least partially between the source and drain regions.   
     
     
         14 . The integrated circuit of  claim 1 , wherein the ratio of the width to the thickness is at least 2, and/or wherein a sum of the width and the thickness is at least 6 nm. 
     
     
         15 . The integrated circuit of  claim 1 , wherein the ratio of the width to the thickness is at least 0.75. 
     
     
         16 . An integrated circuit, comprising:
 a body including silicon;   a gate structure including a gate electrode and a gate dielectric;   a first layer including germanium, the first layer between at least a portion of the body and the gate dielectric;   a second layer including silicon, the second layer compositionally different from the first layer and the gate dielectric, the second layer between at least a portion of the first layer and the gate dielectric; and   a source region and a drain region, the portion of the body at least partially between the source and drain regions.   
     
     
         17 . The integrated circuit of  claim 16 , wherein the first layer comprises between 10 atomic % to 90 atomic % germanium. 
     
     
         18 . The integrated circuit of  claim 16 , wherein the first layer comprises silicon, such that silicon is between 70 atomic % to 30 atomic % of the first layer, and germanium is between 30 atomic % to 70 atomic % of the first layer. 
     
     
         19 . The integrated circuit of  claim 16 , wherein:
 the first layer is laterally between at least a portion of top of the body and the gate dielectric;   the first layer is also laterally between at least a portion of a sidewall of the body and the gate dielectric;   the second layer is laterally between at least the portion of top of the body and the gate dielectric; and   the first layer is absent laterally between at least the portion of the sidewall of the body and the gate dielectric.   
     
     
         20 . The integrated circuit of  claim 16 , wherein the layer has a thickness, wherein the body has a horizontal width, and wherein a ratio of the width to the thickness is at most 4.