Memory device

Abstract

A memory device includes a circuit having an element on a substrate, an interconnection layer above the circuit and that includes a pad electrode having a region for metal wiring bonding, a plurality of electrode layers between the circuit and the interconnection layer and that are stacked in a first direction from the circuit to the interconnection layer, a semiconductor pillar that extends in the first direction, and a storage film between the electrode layers and the semiconductor pillar. The pad electrode overlaps the circuit element as viewed in the first direction.

1 - 3 . (canceled) 
     
     
         4 . A memory device, comprising:
 a circuit comprising a circuit element on a substrate;   an interconnection layer above the circuit and comprising a pad electrode having a region to which a metal bonding wire can be bonded;   a plurality of electrode layers between the circuit and the interconnection layer and stacked in a first direction from the circuit to the interconnection layer;   a semiconductor pillar extending in the first direction; and   a storage film between one of the plurality of electrode layers and the semiconductor pillar, wherein   the pad electrode overlaps the circuit element as viewed in the first direction.   
     
     
         5 . The memory device according to  claim 4 , further comprising:
 a contact plug that extends in the first direction and electrically connects an interconnection in the interconnection layer to the circuit, wherein   the contact plug is located between the pad electrode and the circuit.   
     
     
         6 . The memory device according to  claim 5 , further comprising:
 an insulator between the pad electrode and the circuit, the insulator having a thickness in the first direction greater than a length of the semiconductor pillar in the first direction, wherein   the contact plug penetrates the insulator in the first direction.   
     
     
         7 . The memory device according to  claim 5 , further comprising:
 a conductive layer between the circuit and the plurality of electrode layers and connected to the semiconductor pillar, wherein   the circuit includes an interconnection between the substrate and the conductive layer, and the interconnection is connected to the circuit element, and   the contact plug is electrically connected to the interconnection.   
     
     
         8 . The memory device according to  claim 5 , further comprising:
 a conductive layer between the circuit and the plurality of electrode layers and connected to the semiconductor pillar, wherein   the contact plug penetrates the plurality of electrode layers and the conductive layer.   
     
     
         9 . The memory device according to  claim 4 , further comprising:
 an insulator between the pad electrode and the circuit, the insulator having a thickness in the first direction greater than a length of the semiconductor pillar in the first direction.   
     
     
         10 . The memory device according to  claim 4 , further comprising:
 a conductive layer between the circuit and the plurality of electrode layers, the conductive layer connected to the semiconductor pillar; and   a contact plug that penetrates the plurality of electrode layers and is connected to the conductive layer, wherein   the contact plug is between the circuit and the pad electrode.   
     
     
         11 . The memory device according to  claim 4 , wherein the pad electrode is above a region in the first direction that lacks semiconductor pillars. 
     
     
         12 . The memory device according to  claim 4 , further comprising:
 a semiconductor layer between the circuit and the plurality of electrode layers;   a contact plug that penetrates the plurality of electrode layers in the first direction and is connected to the semiconductor layer, the contact plug being between the circuit and the pad electrode; and   an insulator between the pad electrode and the circuit, the insulator having a thickness in the first direction greater than a length of the contact plug in the first direction, wherein   the contact plug penetrates the insulator in the first direction.   
     
     
         13 . The memory device according to  claim 4 , wherein a bonding wire is bonded to the pad electrode. 
     
     
         14 . A memory device, comprising:
 a circuit including a first circuit element on a substrate;   an interconnection layer above a first part of the circuit and including a pad electrode having a region to which a metal bonding wire can be bonded;   a plurality of electrode layers above a second part of the peripheral circuit, the plurality of electrode layers stacked in a first direction from a level of the circuit to a level of the interconnection layer;   a semiconductor pillar extending in the first direction through the plurality of electrode layers; and   a storage film disposed between one of the plurality of electrode layers and the semiconductor pillar, wherein   the pad electrode overlaps the first circuit element as viewed in the first direction.   
     
     
         15 . The memory device according to  claim 14 , wherein the circuit is a power supply circuit. 
     
     
         16 . The memory device according to  claim 14 , further comprising:
 an insulator between the pad electrode and the circuit and that has a thickness in the first direction that is greater than a length of the semiconductor pillar in the first direction, wherein   the contact plug penetrates the insulator in the first direction.   
     
     
         17 . The memory device according to  claim 14 , further comprising:
 a second pad electrode that overlaps a second circuit element in another circuit as viewed in the first direction.   
     
     
         18 . A memory device, comprising:
 a circuit including transistors on a substrate;   a contact plug being in contact with a transistor of the circuit;   a memory cell array above the circuit in a first direction and comprising a memory cell region and a contact region, the memory cell region comprising a plurality of electrode layers stacked in the first direction and the contact region comprising end portions of the plurality of electrode layers formed in a stair-stepped configuration;   a plurality of semiconductor pillars that penetrate the memory cell array in the first direction;   an interconnection layer above the memory cell array in the first direction; and   a pad electrode having a region to which a metal bonding wire can be bonded, wherein   the pad electrode overlaps a transistor of the circuit as viewed in the first direction.   
     
     
         19 . The memory device of  claim 18 , further comprising:
 an insulator between the pad electrode and the circuit, the insulator having a thickness in the first direction that exceeds a length of the semiconductor pillars in the first direction.   
     
     
         20 . The memory device of  claim 18 , wherein the pad electrode is above the memory cell region and the semiconductor pillars do not overlap the pad electrode as viewed in the first direction. 
     
     
         21 . The memory device of  claim 18 , further comprising:
 a first memory cell array and a second memory cell array stacked in the first direction, wherein   a first semiconductor pillar penetrates the first memory cell array and contacts a second semiconductor pillar that penetrates the second memory cell array.   
     
     
         22 . The memory device of  claim 21 , further comprising:
 an insulator between the pad electrode and the circuit, the insulator having a thickness in the first direction that exceeds the combined length of the first semiconductor pillar and the second semiconductor pillar in the first direction.