In-memory computing device for 8t-sram memory cells

Abstract

An in-memory computing device includes a memory array, a multiple row decoder and a sensing circuit. The memory includes non-destructive memory cells, each of which includes an 8T-SRAM to store a bit of data. Each cell is connected to a read word line and a write word line, both connecting a row of said memory cells, a write bit line and a complementary write bit line, and a read bit line connecting a single column of said memory cells. The multiple row decoder activates at least two read word lines at a same time. The sensing circuit detects a signal on each of the selected read bit lines of multiple selected columns for reading. Each signal is a Boolean function of the stored data in the memory cells in its column activated by the activated read word lines.

What is claimed is: 
     
         1 . An in-memory computing device, comprising:
 a memory array including non-destructive memory cells, each said non-destructive memory cell comprising an 8T-SRAM to store a bit of data, wherein each said non-destructive memory cell is connected to:
 a read word line and a write word line, both connecting a row of said memory cells; 
 a write bit line and a complementary write bit line; and 
 a read bit line, said read bit line connecting a single column of said memory cells; 
   a multiple row decoder to activate at least two read word lines at a same time; and   a sensing circuit to detect a signal on each of said selected read bit lines of multiple selected columns for reading, each said signal being a Boolean function of said stored data in those of said memory cells in its said column activated by said activated read word lines.   
     
     
         2 . The device of  claim 1  and wherein said sensing circuit also comprises a write unit to write the output of said read bit lines to said write bit lines and the complement of said output to said complementary write bit lines of selected cells of said memory array. 
     
     
         3 . The device of  claim 2  and wherein said write unit comprises an inverter to invert the output of said read bit line for said complementary write bit lines. 
     
     
         4 . The device of  claim 1  wherein said in-memory computing device is a CAM or a T-CAM unit.