Multi-input floating-point adder

Abstract

Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

1 . (canceled) 
     
     
         2 . A method performed by a multi-input hardware adder, the method comprising:
 receiving, for each of multiple operands to be added by the multi-input hardware adder, a set of bits that represent the operand;   identifying a given operand to which each other operand is to be aligned;   for any other operand that is not aligned with the given operand, shifting the set of bits that represent the other operand to align the other operand with the given operand;   determining, based on a sticky bit for each other operand, an overall sticky bit value, wherein:
 the overall sticky bit value is zero whenever (i) all of the sticky bits for all of the other operands are zero or (ii) at least two of the other operands have sticky bits that are non-zero and do not match; and 
 the overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit; and 
   determining a sum of the multiple operands using the overall sticky bit value.   
     
     
         3 . The method of  claim 2 , further comprising determining, for each other operand, a value of the sticky bit, wherein the sticky bit for each other operand:
 has a non-zero value when a non-zero value was shifted beyond a least significant position of mantissa bits of the other operand and any precision bits of the other operand to generate a shifted set of bits for the other operand; and   has a sign that matches a sign of the other operand.   
     
     
         4 . The method of  claim 2 , wherein for any operand that is not aligned with a given operand of the multiple operands, shifting the set of bits that represent the operand to align the operand with the given operand comprises shifting the set of bits until a value of an exponent of the operand matches a value of an exponent of the given operand. 
     
     
         5 . The method of  claim 2 , wherein identifying the given operand to which each other operand is to be aligned comprises identifying, as the given operand, the operand having a largest exponent value. 
     
     
         6 . The method of  claim 2 , wherein determining the sum of the multiple operands using the overall sticky bit value comprises determining, based on the overall sticky bit value, whether to round a sum of the operands. 
     
     
         7 . The method of  claim 2 , wherein determining the sum of the multiple operands comprises:
 determining a summation set of bits that represents a sum of the set of bits that represent each operand;   whenever a hidden bit of a mantissa of the summation set of bits is zero, normalizing the mantissa of the summation set of bits by shifting the mantissa of the summation set of bits until the hidden bit is a one; and   determining, based on the mantissa of the summation set of bits and the overall sticky bit value, whether to round a floating-point value represented by the summation set of bits.   
     
     
         8 . The method of  claim 7 , wherein determining whether to round the floating-point value represented by the summation set of bits comprises:
 determining a number of bit positions the mantissa of the summation set of bits were shifted to normalize the mantissa of the summation set of bits; and   whenever the number of bit positions exceeds a number of precision bits of the multi-input hardware adder other than the sticky bit, determining to round the floating-point value represented by the summation set of bits based on the floating-point value represented by the summation set of bits and the overall sticky bit value.   
     
     
         9 . A multi-input hardware adder, comprising:
 multiple inputs configured to receive floating-point operands; and   adder circuitry configured to perform operations comprising:
 receiving, for each of multiple operands to be added by the multi-input hardware adder, a set of bits that represent the operand; 
 identifying a given operand to which each other operand is to be aligned; 
 for any other operand that is not aligned with the given operand, shifting the set of bits that represent the other operand to align the other operand with the given operand; 
 determining, based on a sticky bit for each other operand, an overall sticky bit value, wherein:
 the overall sticky bit value is zero whenever (i) all of the sticky bits for all of the other operands are zero or (ii) at least two of the other operands have sticky bits that are non-zero and do not match; and 
 the overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit; and 
 
 determining a sum of the multiple operands using the overall sticky bit value. 
   
     
     
         10 . The multi-input hardware adder of  claim 9 , wherein the operations comprise determining, for each other operand, a value of the sticky bit, wherein the sticky bit for each other operand:
 has a non-zero value when a non-zero value was shifted beyond a least significant position of mantissa bits of the other operand and any precision bits of the other operand to generate a shifted set of bits for the other operand; and   has a sign that matches a sign of the other operand.   
     
     
         11 . The multi-input hardware adder of  claim 9 , wherein for any operand that is not aligned with a given operand of the multiple operands, shifting the set of bits that represent the operand to align the operand with the given operand comprises shifting the set of bits until a value of an exponent of the operand matches a value of an exponent of the given operand. 
     
     
         12 . The multi-input hardware adder of  claim 9 , wherein identifying the given operand to which each other operand is to be aligned comprises identifying, as the given operand, the operand having a largest exponent value. 
     
     
         13 . The multi-input hardware adder of  claim 9 , wherein determining the sum of the multiple operands using the overall sticky bit value comprises determining, based on the overall sticky bit value, whether to round a sum of the operands. 
     
     
         14 . The multi-input hardware adder of  claim 9 , wherein determining the sum of the multiple operands comprises:
 determining a summation set of bits that represents a sum of the set of bits that represent each operand;   whenever a hidden bit of a mantissa of the summation set of bits is zero, normalizing the mantissa of the summation set of bits by shifting the mantissa of the summation set of bits until the hidden bit is a one; and   determining, based on the mantissa of the summation set of bits and the overall sticky bit value, whether to round a floating-point value represented by the summation set of bits.   
     
     
         15 . The multi-input hardware adder of  claim 14 , wherein determining whether to round the floating-point value represented by the summation set of bits comprises:
 determining a number of bit positions the mantissa of the summation set of bits were shifted to normalize the mantissa of the summation set of bits; and   whenever the number of bit positions exceeds a number of precision bits of the multi-input hardware adder other than the sticky bit, determining to round the floating-point value represented by the summation set of bits based on the floating-point value represented by the summation set of bits and the overall sticky bit value.   
     
     
         16 . A multi-input hardware adder comprising:
 multiple inputs configured to receive floating point operands, each input being configured to receive a set of bits that include a floating-point representation of an operand;   an exponent subtraction and swap component configured to identify a given operand to which each other operand is to be aligned;   one or more shifters configured to, for any other operand that is not aligned with the given operand, shift the set of bits that represent the other operand to align the other operand with the given operand;   a sticky bit calculator configured to determine, based on a sticky bit for each other operand, an overall sticky bit value, wherein:
 the overall sticky bit value is zero whenever (i) all of the sticky bits for all of the other operands are zero or (ii) at least two of the other operands have sticky bits that are non-zero and do not match; and 
 the overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit; and 
   adder circuitry configured to determine a sum of the multiple operands using the overall sticky bit value.   
     
     
         17 . The multi-input hardware adder of  claim 16 , wherein the one or more shifters are configured to determine, for each other operand, a value of the sticky bit, wherein the sticky bit for each other operand:
 has a non-zero value when a non-zero value was shifted beyond a least significant position of mantissa bits of the other operand and any precision bits of the other operand to generate a shifted set of bits for the other operand; and   has a sign that matches a sign of the other operand.   
     
     
         18 . The multi-input hardware adder of  claim 16 , wherein for any operand that is not aligned with a given operand of the multiple operands, shifting the set of bits that represent the operand to align the operand with the given operand comprises shifting the set of bits until a value of an exponent of the operand matches a value of an exponent of the given operand. 
     
     
         19 . The multi-input hardware adder of  claim 16 , wherein identifying the given operand to which each other operand is to be aligned comprises identifying, as the given operand, the operand having a largest exponent value. 
     
     
         20 . The multi-input hardware adder of  claim 16 , wherein determining the sum of the multiple operands using the overall sticky bit value comprises determining, based on the overall sticky bit value, whether to round a sum of the operands. 
     
     
         21 . The multi-input hardware adder of  claim 16 , wherein determining the sum of the multiple operands comprises:
 determining a summation set of bits that represents a sum of the set of bits that represent each operand;   whenever a hidden bit of a mantissa of the summation set of bits is zero, normalizing the mantissa of the summation set of bits by shifting the mantissa of the summation set of bits until the hidden bit is a one; and   determining, based on the mantissa of the summation set of bits and the overall sticky bit value, whether to round a floating-point value represented by the summation set of bits.