Precision High Frequency Phase Adders

Abstract

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

What is claimed is: 
     
         1 . An electronic circuit comprising:
 a multiplier circuit with a first input and a second input and an output; and   a phase locked loop (PLL) circuit comprising:
 a mixer circuit with a first mixer input electrically connected to the output of the multiplier circuit, a second mixer input, and an output; 
 a loop filter having an output and an input electrically connected to the output of the mixer circuit; and 
 a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second mixer input of the mixer circuit. 
   
     
     
         2 . The electronic circuit of  claim 1 , wherein the mixer circuit is a differential mixer circuit. 
     
     
         3 . The electronic circuit of  claim 2 , wherein the mixer circuit is a balanced differential mixer circuit. 
     
     
         4 . The electronic circuit of  claim 1 , wherein the mixer circuit comprises a Gilbert mixer circuit. 
     
     
         5 . The electronic circuit of  claim 1 , wherein the multiplier circuit is a differential multiplier circuit. 
     
     
         6 . The electronic circuit of  claim 5 , wherein the multiplier circuit is a double balanced differential multiplier circuit. 
     
     
         7 . The electronic circuit of  claim 1 , wherein the multiplier circuit comprises a triode interface circuit including a transistor that during operation is biased to operate in a triode region. 
     
     
         8 . The electronic circuit of  claim 7 , wherein the transistor is an MOS transistor. 
     
     
         9 . The electronic circuit of  claim 1 , wherein the multiplier circuit comprises two triode interface circuits electrically connected together, wherein each of the two triode interface circuits includes a transistor that during operation is biased to operate in a triode region. 
     
     
         10 . The electronic circuit of  claim 9 , wherein the two triode interface circuits are electrically connected together to form a double-balanced triode interface configuration. 
     
     
         11 . The electronic circuit of  claim 9 , wherein the transistor in each of the two triode interfaces is an MOS transistor. 
     
     
         12 . The electronic circuit of  claim 1 , wherein the loop filter is a low pass filter. 
     
     
         13 . The electronic circuit of  claim 12 , wherein the PLL circuit further comprises an amplifier connecting output of the mixer circuit to an input of the loop filter. 
     
     
         14 . The electronic circuit of  claim 13 , wherein the amplifier is a folded cascode amplifier. 
     
     
         15 . The electronic circuit of  claim 1 , wherein the PLL circuit further comprises a buffer circuit electrically connecting the output of the VCO circuit to the second mixer input of the mixer circuit. 
     
     
         16 . The electronic circuit of  claim 1 , wherein the first mixer input of the mixer is a differential input having a first input line and a second input line and wherein the output of the VCO circuit is a differential output with a first output line electrically connected to the first input line of the first mixer input of the mixer and a second output line electrically connected to the second input line of the first mixer input of the mixer. 
     
     
         17 . The electronic circuit of  claim 1 , wherein the multiplier circuit and the PLL circuit are fabricated together on a single integrated circuit chip.