Apparatuses and methods for write address tracking

Abstract

Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.

1 - 20 . (canceled) 
     
     
         21 . An apparatus, comprising:
 an array of memory cells;   a cache coupled to the array;   sensing circuitry comprising a plurality of sense amplifiers each coupled to the array; and   a shared input/output (I/O) line shared by each of the plurality of sense amplifiers;   a command interface coupled to the cache and configured to provide commands to the cache along with corresponding column addresses and updated data received through the shared I/O line and to be written to the cache; and   tracking circuitry coupled to the cache, wherein the tracking circuitry is configured to track write addresses of data written to the cache from the shared I/O line.   
     
     
         22 . The apparatus of  claim 21 , further comprising a controller coupled to the cache and configured to:
 send a command for copying cache data from the cache to the array, the command having an associated column address.   
     
     
         23 . The apparatus of  claim 22 , wherein the controller is further configured to transfer data from the shared I/O line to the sensing circuitry and selectably transfer data from the plurality of sense amplifiers to a portion of the array corresponding to a number of columns of memory cells; 
     
     
         24 . The apparatus of  claim 21 , wherein the tracking circuitry comprises latch circuitry and the column addresses are latched in the latch circuitry. 
     
     
         25 . The apparatus of  claim 24 , wherein the tracking circuitry is further configured to track each of the column addresses associated with the updated data received to the cache via the command interface. 
     
     
         26 . The apparatus of  claim 21 , wherein the tracking circuitry is configured to set a flag associated with a first column address in response to updated data associated with the first column address being written to the cache. 
     
     
         27 . The apparatus of  claim 26 , wherein the tracking circuitry further comprises a latch to store a data value that indicates the flag is set. 
     
     
         28 . The apparatus of  claim 26 , wherein the tracking circuitry is configured to not set a flag associated with a second column address in response to data associated with the second column address not being written to the cache. 
     
     
         29 . The apparatus of  claim 21 , wherein the tracking circuitry is configured to latch a data value that corresponds to a column address associated with at least one of the write commands. 
     
     
         30 . A method, comprising:
 writing data stored in an array of memory cells to a cache;   updating a portion of the data stored in the cache, wherein the updated data is transferred via a shared input/output (I/O) line coupled to each of a plurality of sense amplifiers coupled to the array and via a compute component coupled to at least one of the plurality of sense amplifiers;   tracking column addresses associated with the updated portion of the data; and   in response to receiving a write command, from a controller, to copy at least the updated portion of data from the cache to the array, comparing the column addresses associated with the write command with the tracked column addresses.   
     
     
         31 . The method of  claim 30 , further comprising, in response to the column addresses matching the tracked column addresses, writing the updated portion of the data associated with each of the matched column addresses to the array. 
     
     
         32 . The method of  claim 31 , further comprising not writing portions of the data associated with column addresses that do not match. 
     
     
         33 . The method of  claim 30 , further comprising, in response to a command being sent via a command interface to update a portion of the data associated with column addresses and stored in the cache with data received across the shared I/O line, modifying the portion of the data associated with the command. 
     
     
         34 . An apparatus, comprising:
 an array of memory cells;   sensing circuitry comprising a plurality of sense amplifiers each coupled to the array; and   a shared input/output (I/O) line shared by each of the plurality of sense amplifiers;   a controller coupled to a cache and configured to transfer data from the shared I/O line to the sensing circuitry and selectably transfer data from the plurality of sense amplifiers to a portion of the array corresponding to a number of columns of memory cells;   a command interface coupled to the cache and configured to provide commands to the cache along with corresponding column addresses and updated data received through the shared I/O line and to be written to the cache; and   tracking circuitry configured to compare the column address of one of the commands for copying cache data from the cache to the array to tracked addresses associated with the updated data received to the cache via the command interface.   
     
     
         35 . The apparatus of  claim 34 , wherein the controller is a DDR4 SDRAM controller. 
     
     
         36 . The apparatus of  claim 34 , wherein the controller is further configured to, in response to the tracking circuitry matching the column address and one of the tracked addresses, write data associated with the each of the matched column addresses from the cache to the array. 
     
     
         37 . The apparatus of  claim 36 , wherein the controller is further configured to not write data associated with a column address that does not match a tracked address of the tracked addresses. 
     
     
         38 . The apparatus of  claim 34 , wherein the command interface is a DRAM command interface. 
     
     
         39 . The apparatus of  claim 34 , wherein the controller is further configured to cause latching of a value in a latch in response to receiving a write command associated with a column address. 
     
     
         40 . The apparatus of  claim 39 , wherein the controller is further configured to cause:
 writing data associated with the latched value to the array; and   clearing of the latched value in response to the writing of the data associated with the tracked column addresses to the array.