US2020357634A1PendingUtilityA1

Method for Manufacturing a Semiconductor Device

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Sep 29, 2017Filed: Jul 27, 2020Published: Nov 12, 2020
Est. expirySep 29, 2037(~11.2 yrs left)· nominal 20-yr term from priority
H10P 76/4085H10P 76/405H10P 50/695H10P 50/692H10P 50/73H10P 14/6927H10P 14/6339H10P 14/6336H10W 20/085H10W 20/43H10W 20/089H10W 20/081H10P 14/6922H10P 76/4083H10D 30/024H10D 84/0193H10D 84/038C23C 16/45536H01J 37/32082C23C 16/45553H01J 37/32174C23C 16/401C23C 16/0245C23C 16/45529C23C 16/308C23C 14/0676C23C 16/045C23C 16/042C23C 14/228C23C 14/08H01L 21/31144H01L 21/76816H01L 21/76802H01L 21/0214H01L 21/0332H01L 21/02274H01L 21/0337H01L 21/0228H01L 21/3086H01L 21/3081H01L 21/02126H01L 21/823821H01L 29/66795
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Claims

Abstract

A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 depositing a dielectric layer over a substrate;   depositing a masking layer covering the dielectric layer;   performing a patterning on the masking layer to form a recess that exposes a top surface of the dielectric layer, wherein the recess has a first interior width;   depositing an oxide film over the masking layer and within the recess, wherein the oxide film is formed from a plurality of precursors, wherein the precursors of the plurality of precursors are free of allotropes of oxygen, and wherein depositing the oxide film comprises forming a plasma of a first precursor of the plurality of precursors, wherein depositing the oxide film within the recess forms a trench within the recess having a second interior width that is smaller than the first interior width; and   performing an etching process to extend the trench into the dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the sidewalls of the trench within the recess have a roughness that is less than the roughness of the sidewalls of the recess. 
     
     
         3 . The method of  claim 1 , wherein the plurality of precursors includes H 2 O, CO 2 , or H 2 O 2 . 
     
     
         4 . The method of  claim 1 , wherein the oxide film is silicon oxycarbide. 
     
     
         5 . The method of  claim 1 , wherein depositing the oxide film comprises a process temperature of less than 200° C. 
     
     
         6 . The method of  claim 1 , wherein the masking layer comprises a photoresist. 
     
     
         7 . The method of  claim 1 , wherein the oxide film is deposited conformally. 
     
     
         8 . The method  claim 1 , wherein the oxide film has a thickness between 0.1 nm and 100 nm. 
     
     
         9 . A method comprising:
 forming a first dielectric layer over a semiconductor substrate;   forming a second dielectric layer over the first dielectric layer;   forming a third dielectric layer over the second dielectric layer;   patterning the third dielectric layer;   etching openings in the second dielectric layer using the patterned third dielectric layer as an etch mask, wherein the sidewalls of the openings in the second dielectric layer have a first roughness;   depositing a low-temperature dielectric (LTD) layer on the second dielectric layer, wherein the LTD layer extends over a top surface of the second dielectric layer and on the sidewalls of the openings in the second dielectric layer, wherein first portions of the LTD layer on the sidewalls of the openings in the second dielectric layer have a second roughness that is less than the first roughness; and   etching openings in the first dielectric layer using the second dielectric layer and the first portions of the LTD layer as a combined etch mask.   
     
     
         10 . The method of  claim 9 , wherein the LTS layer is an oxide material. 
     
     
         11 . The method of  claim 10 , wherein the third dielectric layer is the oxide material. 
     
     
         12 . The method of  claim 9 , wherein the second dielectric layer is a polymer. 
     
     
         13 . The method of  claim 9 , wherein the openings in the second dielectric layer expose regions of the first dielectric layer, and wherein second portions of the LTD layer cover the regions of the first dielectric layer. 
     
     
         14 . The method of  claim 13 , wherein etching openings in the first dielectric layer comprises etching through the second portions of the LTD layer. 
     
     
         15 . The method of  claim 9 , wherein depositing the LTD layer comprises performing a plasma-enhanced atomic layer deposition (PEALD) process using a plurality of precursors, wherein the plurality of precursors are free of O 2 . 
     
     
         16 . A method comprising:
 forming an inter-layer dielectric (ILD) layer over a semiconductor substrate, the semiconductor substrate comprising an active device;   forming a mask layer over the ILD layer;   patterning the mask layer to form a first opening that exposes the ILD layer, wherein the mask layer has a first width between opposite surfaces of the mask layer within the first opening;   conformally depositing an oxide layer on the mask layer, within the first opening, and on the exposed ILD layer, wherein the oxide layer has a second width between opposite surfaces of the oxide layer within the first opening, wherein the second width is less than the first width; and   performing an etching process to etch through the oxide layer on the exposed ILD layer and into the ILD layer to form a second opening in the ILD layer, wherein the second opening in the ILD layer has the second width between opposite surfaces of the ILD layer within the second opening.   
     
     
         17 . The method of  claim 16 , wherein, after depositing the oxide layer on the mask layer, opposite surfaces of the mask layer within the first opening have third width that is between 0 nm and 50 nm greater than the first width. 
     
     
         18 . The method of  claim 16 , further comprising forming a contact to the active device in the second opening. 
     
     
         19 . The method of  claim 16 , wherein surfaces of oxide layer within the first opening have a smaller edge roughness than surfaces of the mask layer within the first opening. 
     
     
         20 . The method of  claim 16 , wherein conformally depositing the oxide layer comprises forming a plasma from precursors, wherein the precursors are free of allotopes of oxygen.

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