Tamper detection countermeasures to deter physical attack on a security asic

Abstract

Various embodiments of the present invention relates generally to an integrated circuit, and more particularly, to systems, devices and methods of incorporating a tamper detection countermeasure into a security ASIC to deter physical attacks. The tamper detection countermeasure architects an active mesh to cover a sensitive area in the security ASIC. A plurality of time-varying random numbers is generated by a random number generator (RNG), and the active mesh is driven and configured according to these random numbers. During tamper detection cycles, the active mesh is monitored with respect to the plurality of random numbers that is directly provided by the RNG. Upon a tampering attempt, a flag signal is generated and used to initialize subsequent anti-tampering actions. The active mesh may be controlled and monitored based on time-varying codes, and therefore, an adversary may not easily bypass the active mesh and attack the sensitive area.

What is claimed is: 
     
         1 . A tamper detection system to protect sensitive areas in secure application specific integrated circuits (ASICs), the system comprising:
 an active mesh comprising first and second capacitors having substantially equal capacitances;   a random number generator (RNG) to generate first and a second random numbers;   a mesh driver to drive the active mesh with a time-varying configuration according to the first and second random numbers, the first and second capacitors having been selected according to the first and second random numbers; and   a tamper sensing unit coupled to the active mesh to generate, in response to detecting a disparity in the capacitances, a signal indicating a tampering attempt.   
     
     
         2 . The system according to  claim 1 , wherein the RNG generates third and fourth random numbers that are used to select a third and fourth capacitor to be compared for tamper detection during a tamper detection cycle in which the first and second capacitors are monitored. 
     
     
         3 . The system according to  claim 1 , wherein the tamper sensing unit comprises a capacitance comparator. 
     
     
         4 . The system according to  claim 1 , further comprising one or more analog switches that are controlled to couple the plurality of capacitors to the RNG, the mesh driver, and the tamper sensing unit. 
     
     
         5 . The system according to  claim 4 , wherein the active mesh is made from at least one metal layer above a substrate of the secure ASIC and is routed to the substrate via intermediate metal and polysilicon layers. 
     
     
         6 . The system according to  claim 5 , wherein the one or more analog switches are located at least partially within the substrate. 
     
     
         7 . A method of detecting a tampering attempt in a secure application specific integrated circuit (ASIC), the method comprising steps of:
 generating a plurality of random numbers;   configuring and driving an active mesh according to the plurality of random numbers, the active mesh covering a sensitive area in a secure ASIC;   monitoring the active mesh with respect to the plurality of random numbers; and   generating a signal that indicates a tampering attempt.   
     
     
         8 . The system according to  claim 7 , wherein the active mesh comprises an array of resistors configured to form a resistor bridge. 
     
     
         9 . The method according to  claim 7 , wherein the active mesh is formed by at least one metal layer above a substrate of the secure ASIC and is routed to the substrate via intermediate metal and polysilicon layers. 
     
     
         10 . The method according to  claim 7 , wherein the active mesh comprises a plurality of capacitors or metal wires, and the plurality of random numbers comprises a first random number and a second random number. 
     
     
         11 . The method according to  claim 10 , further comprising selecting, according to the first and second random numbers, first and second capacitors or first and second metal wires from the plurality of capacitors or metal wires. 
     
     
         12 . The method according to  claim 11 , wherein monitoring the active mesh comprises steps comprising:
 comparing capacitances of the first and second capacitors or metal wires; and   in response to determining a disparity in the capacitances, generating the signal.   
     
     
         13 . The method according to  claim 10 , wherein at least one random number in the plurality of random numbers comprises a plurality of bits, and the step of configuring and driving the active mesh further comprises driving a first end node of each of the plurality of capacitors or metal wires at a logic level that is determined by a bit in the plurality of bits. 
     
     
         14 . The method according to  claim 13 , wherein monitoring the active mesh further comprises steps comprising:
 monitoring a voltage at a second end node of at least one metal wire or capacitor selected from the plurality of capacitors or metal wires;   verifying the voltage with respect to a corresponding bit in the plurality of bits; and   generating the signal.   
     
     
         15 . A tamper detection system for protecting a sensitive area in a secure application specific integrated circuit (ASIC), the system comprising:
 an active mesh comprising one of a capacitor or a metal wire that serves as an electrode;   a substrate coupled to the active mesh;   a metal layer coupled to the substrate to form a counter-electrode;   a random number generator (RNG) to generate a set of random numbers comprising a plurality of bits;   a mesh driver to drive the active mesh with a time-varying driving pattern according to the set of random numbers, a first end node of the capacitor or metal wire being driven at a logic level determined by a bit in the plurality of bits; and   a tamper sensing unit coupled to the active mesh and the RNG to perform steps comprising:
 monitoring a voltage at a second end node of the capacitor or metal wire; 
 verifying the voltage with respect to a corresponding bit in the plurality of bits; and 
 generating a signal that indicates a tampering attempt. 
   
     
     
         16 . The system according to  claim 15 , wherein the active mesh comprises an array of resistors configured to form resistive stings. 
     
     
         17 . The system according to  claim 15 , wherein the active mesh comprises an array of resistors configured to form a resistor bridge. 
     
     
         18 . The system according to  claim 15 , wherein the mesh driver further comprises a state machine to control a temporal variation of the time-varying driving pattern. 
     
     
         19 . The system according to  claim 15 , further comprising at least one of a cache memory and a data register to temporarily store the set of random numbers. 
     
     
         20 . The system according to  claim 15 , further comprising a plurality of analog switches that are controlled to couple the capacitor or metal wire to the RNG, the mesh driver, and the tamper sensing unit.