Memory module and memory system having the same

Abstract

A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.

What is claimed is: 
     
         1 . A memory module, comprising:
 a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID;   a power management unit (PMU) responsive to at least one of the module ID and the register address generated by the SPD, the PMU configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal; and   a plurality of semiconductor memory devices configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.   
     
     
         2 . The memory module of  claim 1 , further comprising:
 a temperature sensor (TS) communicatively coupled to the SPD; and   a register clock driver (RCD) communicatively coupled to the SPD, the RCD configured to receive and transmit the command/address signals to the plurality of semiconductor memory devices.   
     
     
         3 . The memory module of  claim 2 , wherein the SPD is communicatively coupled by a local data communication channel to the PMU, RCD and TS; and wherein the local data communication channel transmits at least one of the module ID and the register address corresponding to the module ID in series in response to a local serial clock signal. 
     
     
         4 . The memory module of  claim 1 , wherein the PMU comprises:
 a register unit including a module ID register for storing the module ID, and a plurality of control data registers for storing a plurality of pieces of different control data corresponding to a plurality of different module IDs; and   an internal clock signal generator configured to generate the internal clock signal having the on-time point and/or the off-time point set in response to the control data generated from one corresponding to the at least one of the module ID and the register address corresponding to the module ID among the plurality of control data registers.   
     
     
         5 . The memory module of  claim 1 , wherein the SPD is configured to support global data communication with an external device, receive the register address corresponding to the module ID, perform local data communication with the PMU, and transmit the register address corresponding to the module ID. 
     
     
         6 . The memory module of  claim 5 , wherein the PMU comprises:
 a register unit including a module ID register for storing the module ID, and a plurality of control data registers for storing a plurality of pieces of different control data corresponding to a plurality of different module IDs; and   an internal clock signal generator configured to generate the internal clock signal having the on-time point and/or the off-time point set in response to the control data generated from one corresponding to the register address corresponding to the module ID among the plurality of control data registers.   
     
     
         7 . The memory module of  claim 6 , wherein the global data communication provides the register address corresponding to the module ID in series, in response to a global serial clock signal. 
     
     
         8 . A memory module, comprising:
 a power management unit (PMU) configured to set an on-time point and/or an off-time point of an internal clock signal based on a module ID, and generate at least one internal power supply voltage in response to the internal clock signal; and   a plurality of semiconductor memory devices configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.   
     
     
         9 . The memory module of  claim 8 , further comprising:
 a temperature sensor (TS) communicatively coupled to the PMU; and   a register clock driver (RCD) communicatively coupled to the PMU, the RCD configured to receive and transmit the command/address signals to the plurality of semiconductor memory devices.   
     
     
         10 . The memory module of  claim 8 , wherein the PMU detects the module ID through at least one module position identification terminal, and generates at least one of the module ID and a register address corresponding to the module ID. 
     
     
         11 . The memory module of  claim 10 , wherein the PMU comprises:
 a register unit including a plurality of control data registers for storing a plurality of pieces of different control data corresponding to a plurality of different module IDs; and   an internal clock signal generator configured to generate the internal clock signal having the on-time point and/or the off-time point set in response to the control data generated from one corresponding to the at least one of the module ID and the register address corresponding to the module ID among the plurality of control data registers.   
     
     
         12 . The memory module of  claim 8 , wherein the PMU is configured to support global data communication with an external device, and receive a register address corresponding to the module ID. 
     
     
         13 . The memory module of  claim 12 , wherein the PMU comprises:
 a register unit including a plurality of control data registers for storing a plurality of pieces of different control data corresponding to a plurality of different module IDs; and   an internal clock signal generator configured to generate the internal clock signal having the on-time point and/or the off-time point set in response to the control data generated from one corresponding to the register address corresponding to the module ID among the plurality of control data registers.   
     
     
         14 . A memory system, comprising:
 a main board having a plurality of memory slots therein;   a plurality of memory modules mounted in the plurality of memory slots; and   a control unit configured to perform global data communication with the plurality of memory modules, transmit a command/address, and transmit and receive data;   wherein each of the plurality of memory modules comprises:
 a power management unit (PMU) configured to set an on-time point and/or an off-time point of an internal clock signal based on a corresponding module ID among a plurality of module IDs different from each other, and generate at least one internal power supply voltage in response to the internal clock signal; and 
 a plurality of semiconductor memory devices configured to receive the at least one internal power supply voltage, and perform an operation in response to the command/address. 
   
     
     
         15 . The memory system of  claim 14 , wherein each of the plurality of memory modules further comprises:
 a serial presence detector (SPD) configured to transmit at least one of the module ID and a register address corresponding to the module ID by performing local data communication with the PMU when detecting the module ID through at least one module position identification terminal, or transmit the register address corresponding to the module ID by performing the local data communication with the PMU when receiving the register address corresponding to the module ID by performing the global data communication.   
     
     
         16 . The memory system of  claim 15 , wherein the local data communication transmits the at least one of the module ID and the register address corresponding to the module ID in series in response to a local serial clock signal, and wherein the global data communication transmits the register address corresponding to the module ID in series in response to a global serial clock signal. 
     
     
         17 . The memory system of  claim 15 , wherein each of the plurality of memory modules comprises:
 a temperature sensor configured to sense a temperature, and perform the local data communication with the SPD; and   a register clock driver configured to receive the command/address to transmit a command/address signal to the plurality of semiconductor memory devices, and perform the local data communication with the SPD.   
     
     
         18 . The memory system of  claim 14 , wherein the PMU is configured to generate the at least of the module ID and the register address corresponding to the module ID when detecting the module ID through at least one module position identification terminal, or generate the register address corresponding to the module ID when receiving the register address corresponding to the module ID by performing the global data communication. 
     
     
         19 . The memory system of  claim 18 , wherein each of the plurality of memory modules comprises:
 a temperature sensor configured to sense a temperature, and perform local data communication with the PMU; and   a register clock driver configured to receive the command/address to transmit a command/address signal to the plurality of semiconductor memory devices, and perform the local data communication with the PMU.   
     
     
         20 . The memory system of  claim 14 , wherein the PMU further comprises:
 a register unit including a module ID register for storing the module ID, and a plurality of control data registers for storing a plurality of pieces of control data different from each other corresponding to a plurality of module IDs; and   an internal clock signal generator configured to generate the internal clock signal having the on-time point and/or the off-time point set in response to the control data generated from one corresponding to the at least of the module ID and the register address corresponding to the module ID among the plurality of control data registers.