Encoding data in a modified-memory system

Abstract

Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated circuits (ICs) is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional RAM ICs, and accordingly the RAM ICs can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified RAM ICs and a traditional memory controller, additionally contains DBI encoding and decoding circuitry. In such a system, data is DBI encoded and at least one DBI bit issued when writing to the modified RAM ICs. The RAM ICs in turn store the DBI bit(s) with the encoded data. When the encoded data is read from the modified RAM ICs, it is transmitted across the bus in its encoded state along with the DBI bit(s). The logic integrated circuit then decodes the data using the DBI bit(s) to return it to its original state.

1 . (canceled) 
     
     
         2 . A device comprising:
 a logic circuit communicatively coupled to a memory controller using a first bus and a memory circuit using a second bus, the logic circuit configured to perform operations comprising:
 receiving a set of N original data bits from the memory controller over the first bus; 
 selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits; 
 generating an encoding indicator associated with the set of N encoded data bits; and 
 transmitting the set of N encoded data bits and the encoding indicator to a memory circuit over the second bus to cause the memory circuit to store the set of N encoded data bits and the encoding indicator in the memory circuit, the memory circuit a separate circuit than the logic circuit. 
   
     
     
         3 . The device of  claim 2 , wherein the logic circuit is further configured to perform the operations comprising:
 receiving the set of N encoded data bits and the encoding indicator from the memory circuit;   decoding the set of N encoded data bits using the encoding indicator to recover the set of N original data bits; and   transmitting the set of N original data bits to the memory controller over the first bus.   
     
     
         4 . The device of  claim 2 , wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises selectively encoding the set of N original data bits based upon a set of previously processed data bits sent over the second bus. 
     
     
         5 . The device of  claim 4 , wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises applying a data bit inversion (DBI) to minimize a number of bit transitions between the set of N encoded bits and the set of previously processed data bits. 
     
     
         6 . The device of  claim 2 , wherein the operations of receiving the set of N original data bits comprises a write request to write the set of N original data bits to the memory circuit. 
     
     
         7 . The device of  claim 2 , wherein the memory circuit is a random-access memory circuit. 
     
     
         8 . The device of  claim 2 , wherein the logic circuit includes one or more of: command decode circuitry; queueing circuitry; redundancy circuitry; error correction circuitry; test mode circuitry; or integration circuitry. 
     
     
         9 . A method comprising:
 at a logic circuit communicatively coupled to a memory controller using a first bus and a memory circuit using a second bus, performing operations of:   receiving a set of N original data bits from the memory controller over the first bus;   selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits;   generating an encoding indicator associated with the set of N encoded data bits; and   transmitting the set of N encoded data bits and the encoding indicator to a memory circuit over the second bus to cause the memory circuit to store the set of N encoded data bits and the encoding indicator in the memory circuit, the memory circuit a separate circuit than the logic circuit.   
     
     
         10 . The method of  claim 9 , wherein the logic circuit is further configured to perform the operations comprising:
 receiving the set of N encoded data bits and the encoding indicator from the memory circuit;   decoding the set of N encoded data bits using the encoding indicator to recover the set of N original data bits; and   transmitting the set of N original data bits to the memory controller over the first bus.   
     
     
         11 . The method of  claim 9 , wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises selectively encoding the set of N original data bits based upon a set of previously processed data bits sent over the second bus. 
     
     
         12 . The method of  claim 11 , wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises applying a data bit inversion (DBI) to minimize a number of bit transitions between the set of N encoded bits and the set of previously processed data bits. 
     
     
         13 . The method of  claim 9 , wherein the operations of receiving the set of N original data bits comprises a write request to write the set of N original data bits to the memory circuit. 
     
     
         14 . The method of  claim 9 , wherein the memory circuit is a random-access memory circuit. 
     
     
         15 . The method of  claim 9 , wherein the logic circuit includes one or more of: command decode circuitry; queueing circuitry; redundancy circuitry; error correction circuitry; test mode circuitry; or integration circuitry. 
     
     
         16 . A memory system comprising:
 a memory controller;   a memory circuit;   a logic circuit interposed between the memory controller and the memory circuit, the logic circuit communicatively coupled to the memory controller using a first bus and the memory circuit using a second bus, the logic circuit comprising:
 receiving a set of N original data bits from the memory controller over the first bus; 
 selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits; 
 generating an encoding indicator associated with the set of N encoded data bits; and 
 transmitting the set of N encoded data bits and the encoding indicator to a memory circuit over the second bus to cause the memory circuit to store the set of N encoded data bits and the encoding indicator in the memory circuit, the memory circuit a separate circuit than the logic circuit. 
   
     
     
         17 . The memory system of  claim 16 , wherein the logic circuit is further configured to perform the operations comprising:
 receiving the set of N encoded data bits and the encoding indicator from the memory circuit;   decoding the set of N encoded data bits using the encoding indicator to recover the set of N original data bits; and   transmitting the set of N original data bits to the memory controller over the first bus.   
     
     
         18 . The memory system of  claim 16 , wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises selectively encoding the set of N original data bits based upon a set of previously processed data bits sent over the second bus. 
     
     
         19 . The memory system of  claim 18 , wherein the operations of selectively encoding the set of N original data bits to form a corresponding set of N encoded data bits comprises applying a data bit inversion (DBI) to minimize a number of bit transitions between the set of N encoded bits and the set of previously processed data bits. 
     
     
         20 . The memory system of  claim 16 , wherein the operations of receiving the set of N original data bits comprises a write request to write the set of N original data bits to the memory circuit. 
     
     
         21 . The memory system of  claim 16 , wherein the memory circuit is a random-access memory circuit.