Selectively disabled output

Abstract

Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a field programmable gate array (FPGA) fabric that is programmable based at least in part on configuration data stored in configuration memory;   a controller configured to program the FPGA fabric by writing the configuration data to the configuration memory, wherein the controller is configured to:
 receive encrypted data; and 
 determine the configuration data by decrypting the encrypted data based on an encryption key; and 
   a non-volatile memory communicatively coupled to the controller, wherein a portion of the non-volatile memory contains the encryption key;   an input pad configured to couple to a system high voltage or a system low voltage, wherein the configuration data cannot be read from the configuration memory when the input pad is coupled to the system high voltage; and   one-time programmable memory configured to selectably permanently write-protect the encryption key.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the one-time programmable memory is configured to selectably permanently disable external access to the encryption key. 
     
     
         3 . The integrated circuit device of  claim 1 , wherein the one-time programmable memory is configured to selectably permanently disable erasure of the encryption key. 
     
     
         4 . The integrated circuit device of  claim 1 , wherein the one-time programmable memory is configured to selectably permanently disable debugging of the integrated circuit device. 
     
     
         5 . The integrated circuit device of  claim 1 , wherein the one-time programmable memory is configured to selectably permanently disable access to internal data of the integrated circuit device other than configuration data or the encryption key that otherwise could be accessed. 
     
     
         6 . The integrated circuit device of  claim 1 , wherein the one-time programmable memory is configured to be activated to permanently disable access post-manufacturing. 
     
     
         7 . The integrated circuit device of  claim 1 , wherein the one-time programmable memory is configured to selectably permanently disable reading of internal data. 
     
     
         8 . A method for operating a programmable logic device comprising a field programmable gate array (FPGA) fabric, comprising:
 storing an encryption key into the programmable logic device, thereby enabling a controller in the programmable logic device to decrypt an encrypted bitstream of configuration data and program the configuration data into configuration memory that controls functionality of the field programmable gate array (FPGA) fabric; and   programming a one-time programmable memory to permanently disable external access to the encryption key, wherein the configuration data is stored in configuration data memory, and wherein an input pad configured to couple to a system high voltage or a system low voltage causes the configuration data to be inaccessible in the configuration data memory when the input pad is coupled to the system high voltage.   
     
     
         9 . The method of  claim 8 , wherein the encryption key is stored into non-volatile memory in the programmable logic device. 
     
     
         10 . The method of  claim 8 , wherein programming the one-time programmable memory to permanently disable external access to the encryption key comprises permanently disabling write access to the encryption key. 
     
     
         11 . The method of  claim 8 , wherein programming the one-time programmable memory to permanently disable external access to the encryption key comprises permanently disabling erasure of the encryption key. 
     
     
         12 . The method of  claim 8 , wherein programming the one-time programmable memory takes place post-manufacturing. 
     
     
         13 . The method of  claim 8 , wherein programming the one-time programmable memory comprises permanently disabling debugging of the programmable logic device. 
     
     
         14 . The method of  claim 8 , wherein programming the one-time programmable memory permanently disables external access to an area of internal data of the programmable logic device. 
     
     
         15 . An electronic device comprising memory that stores instructions executable by one or more processors to control a programmable logic device post-manufacturing, wherein the instructions include instructions to:
 inject a user encryption key into a programmable logic device communicatively coupled to the electronic device;   instruct the programmable logic device communicatively coupled to the electronic device to permanently disable erasure of the user encryption key; and   communicate encrypted data from the electronic device to the programmable logic device to enable a controller in the programmable logic device to decrypt the encrypted data to obtain configuration data for a field programmable gate array (FPGA) fabric of the programmable logic device,   instruct the programmable logic device to store the configuration data in configuration data memory, wherein an input pad of the programmable logic device is configured to couple to a system high voltage or a system low voltage, and wherein the configuration data is inaccessible from the configuration data memory when the input pad is coupled to the system high voltage.   
     
     
         16 . The electronic device of  claim 15 , wherein the instructions to inject the user encryption key comprise instructions to inject the user encryption key into a non-volatile memory of the programmable logic device communicatively coupled to the electronic device. 
     
     
         17 . The electronic device of  claim 15 , wherein the instructions to permanently disable erasure of the user encryption key comprise instructions to permanently disable write access to the user encryption key. 
     
     
         18 . The electronic device of  claim 15 , wherein the instructions comprise instructions to permanently disable external access to the user encryption key. 
     
     
         19 . The electronic device of  claim 15 , wherein the instructions comprise instructions to permanently disable debugging of the programmable logic device. 
     
     
         20 . The electronic device of  claim 15 , wherein the instructions to permanently disable erasure of the user encryption key comprise instructions to program a one-time programmable memory of the programmable logic device that permanently disables write access to the user encryption key.