Semiconductor device having polysilicon field plate for power mosfets

Abstract

A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

1 . A method of fabricating a semiconductor device, comprising:
 forming a trench for a field plate (FP) in a semiconductor layer of a substrate;   forming a dielectric liner in the trench;   forming photoresist over the substrate including over the dielectric liner within the trench;   exposing and then developing the photoresist to remove the photoresist in an upper portion of the trench so that the photoresist remains in a lower portion of the trench;   etching the dielectric liner in the upper portion of the trench while the dielectric liner layer in the lower portion of the trench is protected by the photoresist;   removing the photoresist from the lower portion of the trench;   filling the trench with a single polysilicon layer, and   forming a power metal-oxide-semiconductor field effect transistor (power MOSFET) adjacent to the FP, the power MOSFET including a vertical drift region in the semiconductor surface layer above a drain including a drain contact, a gate, a body, and a source above the vertical drift region.   
     
     
         2 . The method of  claim 1 , wherein the dielectric liner includes a thermally grown silicon oxide layer underlying a sub-atmospheric chemical vapor deposition (SACVD) deposited silicon dioxide layer, and wherein the dielectric liner in the lower portion of the trench is at least 50% thicker as compared to a the dielectric liner in the upper portion of the trench after etching the dielectric liner. 
     
     
         3 . A method of fabricating a semiconductor device, comprising:
 forming a trench for a field plate (FP) in a semiconductor surface layer of a substrate;   dielectric lining the trench with a dielectric liner including a first dielectric liner layer and then depositing a second dielectric liner layer on the first dielectric liner layer;   coating the substrate with photoresist (PR) including filling the trench;   exposing and then developing the PR to remove the PR in an upper portion of the trench so that the PR remains in a lower portion of the trench;   etching to remove the second dielectric liner layer in the upper portion of the trench, wherein the second dielectric liner layer and the first dielectric liner layer in the lower portion of the trench are both protected by the PR;   stripping the PR;   filling the trench by depositing a single polysilicon layer, and   forming a power metal-oxide-semiconductor field effect transistor (power MOSFET) adjacent to the FP, the power MOSFET including a vertical drift region in the semiconductor surface layer above a drain including a drain contact, a gate, a body, and a source above the vertical drift region.   
     
     
         4 . The method of  claim 3 , wherein the second dielectric liner layer has a lower density as compared to the first dielectric liner layer. 
     
     
         5 . The method of  claim 4 , wherein the first dielectric liner layer comprises a thermally grown silicon oxide layer and wherein the second dielectric liner layer comprises a sub-atmospheric chemical vapor deposition (SACVD) deposited silicon dioxide layer, and wherein the dielectric liner in the lower portion of the trench is at least 50% thicker as compared to a thickness of the dielectric liner in the upper portion of the trench. 
     
     
         6 . The method of  claim 3 , wherein the power MOSFET comprises a trench gate MOSFET. 
     
     
         7 . The method of  claim 3 , wherein the power MOSFET comprises a planar gate MOSFET. 
     
     
         8 . The method of  claim 3 , wherein the developing removes 20% to 80% of a height of the PR in the trench. 
     
     
         9 . The method of  claim 8 , wherein the developing removes 40% to 60% of the height of the PR in the trench. 
     
     
         10 . The method of  claim 3 , wherein the FP comprises a first FP and a second FP on opposite sides of the power MOSFET. 
     
     
         11 . The method of  claim 3 , wherein after the depositing the first dielectric liner layer is 50 nm to 300 nm and the second dielectric liner layer is 80 nm to 500 nm. 
     
     
         12 . The method of  claim 3 , wherein the forming the trench further comprises forming an auxiliary trench for an auxiliary FP, wherein the auxiliary trench is filled with the single polysilicon layer and disposed in the semiconductor surface layer lateral to the FP, wherein the exposing and then developing does not remove the PR in the auxiliary trench, and wherein the method further comprises forming a source electrode comprising a metal coupled to the source and to the single polysilicon layer in the FP, and to the single polysilicon layer in the auxiliary trench. 
     
     
         13 . A semiconductor device, comprising:
 a substrate including a semiconductor surface layer;   a field plate (FP) comprising a trench in the semiconductor surface layer filled with a single polysilicon layer on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET), the FP comprising:
 a dielectric liner lining a sidewall of the trench under the single polysilicon layer comprising a second dielectric liner on a first dielectric liner, an upper portion of the dielectric liner having a lower dielectric thickness as compared to a dielectric thickness on a lower portion of the dielectric liner, 
   wherein the single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion, and   wherein the power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, a body and a source above the vertical drift region.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the second dielectric liner layer has a lower density as compared to the first dielectric liner layer. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the first dielectric liner layer comprises a thermal silicon oxide layer. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the power MOSFET comprises a trench gate MOSFET. 
     
     
         17 . The semiconductor device of  claim 13 , wherein the power MOSFET comprises a planar gate MOSFET. 
     
     
         18 . The semiconductor device of  claim 13 , wherein the FP comprises a first FP and a second FP on opposite sides of the power MOSFET. 
     
     
         19 . The semiconductor device of  claim 13 , further comprising:
 an auxiliary FP comprising an auxiliary trench filled with the single polysilicon layer disposed in the semiconductor surface layer lateral to the FP, and   a source electrode comprising a metal coupled to the source and to the single polysilicon layer in the FP and to the single polysilicon layer in the auxiliary FP.   
     
     
         20 . The semiconductor device of  claim 13 , wherein the lower portion is at least 50% thicker as compared to a thickness of the upper portion.