Method of forming a plurality of electronic component packages and packages formed thereby

Abstract

A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.

1 - 20 . (canceled) 
     
     
         21 . A method of forming an electronic component package, the method comprising:
 providing a plurality of integrated circuit (IC) chips attached to a carrier at a spacing no more than W apart in a first direction, wherein each of the IC chips has a height dimension of at least H and a width dimension in the first direction greater than H, and the ratio of H to W is at least four;   laminating a dielectric sheet around the IC chips, said laminating comprising pressing the dielectric sheet onto the IC chips to cause the dielectric sheet to flow around the IC chips and to fill the spaces between the IC chips, wherein:
 the dielectric sheet forms a package body surrounding the IC chips; and 
 the package body comprises a thickness of at least the height dimension of the IC chips for those portions of the package body in the spaces between the IC chips; 
   removing the carrier;   forming a buildup dielectric layer on a respective active side of each of the IC chips and on the package body;   forming a circuit pattern on the buildup dielectric layer; and   cutting at least the package body and the buildup dielectric layer to singulate the electronic component package.   
     
     
         22 . The method of  claim 21 , wherein the package body formed by the dielectric sheet encloses at least five sides of each of the IC chips. 
     
     
         23 . The method of  claim 22 , wherein the at least five sides of each of the IC chips comprise four lateral sides and an inactive side of each of the IC chips. 
     
     
         24 . The method of  claim 21 , wherein H is no greater than 500 μm. 
     
     
         25 . The method of  claim 21 , further comprising:
 forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;   forming a second circuit pattern on the second buildup dielectric layer, where the second circuit pattern is electrically connected to the circuit pattern; and   attaching a package interconnection structure to the second circuit pattern at a location directly vertically aligned with one of the IC chips, wherein there is no conductive path directly vertically between the package interconnection structure and said one of the IC chips.   
     
     
         26 . A method of forming an electronic component package, the method comprising:
 providing an integrated circuit (IC) chip attached to a carrier, wherein the IC chip comprises an active side, and a bond pad on the active side;   forming a package body surrounding the IC chip, wherein said forming the package body comprises laminating a dielectric sheet comprising mold compound around the IC chip, said laminating comprising pressing the dielectric sheet onto the IC chip to cause the dielectric sheet to flow around the IC chip;   removing the carrier; and   forming a signal distribution structure on the active side of the IC chip and on the package body, the signal distribution structure comprising:
 a first conductor coupled to the bond pad of the IC chip, and extending laterally in a first direction to a first position outside of a footprint of the IC chip; 
 a second conductor coupled to the first conductor at the first position outside of the footprint of the IC chip, and extending laterally in a second direction, different from the first direction, to a second position; and 
 a land coupled to the second conductor at the second position. 
   
     
     
         27 . The method of  claim 26 , wherein a lateral distance between the land and a center of the footprint of the IC chip is less than a lateral distance between the bond pad and the center of the footprint of the IC chip. 
     
     
         28 . The method of  claim 26 , wherein the second position is inside of the footprint of the IC chip. 
     
     
         29 . The method of  claim 26 , wherein the signal distribution structure comprises a first dielectric layer that comprises a first via hole through which the first conductor is coupled to the bond pad, and no laterally-running traces extend through the first dielectric layer. 
     
     
         30 . The method of  claim 29 , wherein the first conductor runs through the first via hole to the bond pad. 
     
     
         31 . The method of  claim 30 , wherein:
 the signal distribution structure comprises a second dielectric layer that laterally surrounds the first conductor and comprises a second via hole through which the second conductor is connected to the first conductor;   the second conductor runs through the second via hole to the first conductor; and   the signal distribution structure comprises a third dielectric layer, wherein both second dielectric layer and the third dielectric layer laterally surround the second conductor.   
     
     
         32 . The method of  claim 26 , wherein at least a portion of the land is positioned directly vertically below the bond pad, and no conductive path extends directly vertically between the land and the bond pad. 
     
     
         33 . An electronic component package comprising:
 an integrated circuit (IC) chip comprising:
 an active side; and 
 a bond pad on the active side; 
   a package body surrounding the IC chip;   a signal distribution structure on the active side of the IC chip and on the package body, the signal distribution structure comprising:
 a first conductor coupled to the bond pad, and extending laterally to at least a first position outside of a footprint of the IC chip; 
 a second conductor coupled to the first conductor at the first position outside of the footprint of the IC chip, and extending laterally in a second direction, different from the first direction, to a second position; and 
 a land coupled to the second conductive layer at the second position. 
   
     
     
         34 . The electronic component package of  claim 33 , wherein the package body comprises a dielectric sheet comprising mold compound pressed around the IC chip. 
     
     
         35 . The electronic component package of  claim 33 , wherein a lateral distance between the land and a center of the footprint of the IC chip is less than a lateral distance between the bond pad and the center of the footprint of the IC chip. 
     
     
         36 . The electronic component package of  claim 33 , wherein the second position is inside of the footprint of the IC chip. 
     
     
         37 . The electronic component package of  claim 33 , wherein the signal distribution structure comprises a first dielectric layer that comprises a first via hole through which the first conductor is coupled to the bond pad, and no laterally-running traces extend through the first dielectric layer. 
     
     
         38 . The electronic component package of  claim 37 , wherein the first conductor runs through the first via hole to the bond pad. 
     
     
         39 . The electronic component package of  claim 38 , wherein:
 the signal distribution structure comprises a second dielectric layer that laterally surrounds the first conductor and comprises a second via hole through which the second conductor is connected to the first conductor;   the second conductor runs through the second via hole to the first conductor; and   the signal distribution structure comprises a third dielectric layer, wherein both second dielectric layer and the third dielectric layer laterally surround the second conductor.   
     
     
         40 . The method of  claim 33 , wherein at least a portion of the land is positioned directly vertically below the bond pad, and no conductive path extends directly vertically between the land and the bond pad.