Securely exposing an accelerator to privileged system components

Abstract

Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

What is claimed is: 
     
         1 . An apparatus, comprising circuitry, the circuitry arranged to:
 receive, from a hardware accelerator, an instruction including an indication of a privileged component;   determine whether the instruction is invalid; and   apply a restriction to the instruction based on a determination that the instruction is invalid.   
     
     
         2 . The apparatus of  claim 1 , the circuitry to determine whether the instruction is invalid based on at least one of:
 a protocol validation operation;   a network address permission check;   a memory address range permission check;   an amount of bandwidth used by the hardware accelerator;   an amount of thermal energy generated by the hardware accelerator; or   an amount of power used by the hardware accelerator.   
     
     
         3 . The apparatus of  claim 1 , the circuitry to forward the instruction to the privileged component based on a determination that the instruction is valid. 
     
     
         4 . The apparatus of  claim 1 , the circuitry to, at least one of the following:
 send a control signal to the hardware accelerator to cause the hardware accelerator to reset based on a determination that the instruction is invalid;   create an entry in a system log based on a determination that the instruction is invalid, the entry comprising an indication of the instruction;   generate and transmit a notification based on a determination that the instruction is invalid, the notification comprising an indication of the instruction;   report the instruction via an application programming interface (API) based on a determination that the instruction is invalid; or   send a control signal to the hardware accelerator to cause the hardware accelerator to enter a low power state based on a determination that the instruction is invalid.   
     
     
         5 . The apparatus of  claim 1 , the circuitry comprising a first interface to couple to the and the privileged component and a second interface to couple to the hardware accelerator. 
     
     
         6 . The apparatus of  claim 1 , the circuitry to:
 determine whether the hardware accelerator has responded to a Peripheral Component Interconnect Express (PCIe) request from the privileged component;   generate a response to the PCIe request from the privileged component on behalf of the hardware accelerator based on a determination that the hardware accelerator has not responded to the PCIe request from the privileged component; and   transmit the response to the privileged component.   
     
     
         7 . The apparatus of  claim 1 , circuitry to restrict the hardware accelerator from initiating Peripheral Component Interconnect Express (PCIe) transactions with the privileged component. 
     
     
         8 . The apparatus of  claim 1 , wherein the instruction is associated with an untrusted third party accessing the hardware accelerator in a cloud computing environment. 
     
     
         9 . At least one non-transitory computer-readable medium, comprising instructions that when executed by a security broker coupled to a hardware accelerator and a privileged component, cause the security broker to:
 determine whether an instruction received from the hardware accelerator is invalid, the instruction comprising an indication of the privileged component; and   apply a restriction to the instruction based on a determination that the instruction is invalid.   
     
     
         10 . The at least one non-transitory computer-readable medium of  claim 9 , the instructions, when executed further cause the security broker to determine whether the instruction is invalid based on at least one of:
 a protocol validation operation;   a network address permission check;   a memory address range permission check;   an amount of bandwidth used by the hardware accelerator;   an amount of thermal energy generated by the hardware accelerator; or   an amount of power used by the hardware accelerator.   
     
     
         11 . The at least one non-transitory computer-readable medium of  claim 9 , the instructions, when executed further cause the security broker to forward the instruction to the privileged component based on a determination that the instruction is valid. 
     
     
         12 . The at least one non-transitory computer-readable medium of  claim 9 , the instructions, when executed further cause the security broker to:
 send a control signal to the hardware accelerator to cause the hardware accelerator to reset based on a determination that the instruction is invalid;   create an entry in a system log based on a determination that the instruction is invalid, the entry comprising an indication of the instruction;   generate and transmit a notification based on a determination that the instruction is invalid, the notification comprising an indication of the instruction;   report the instruction via an application programming interface (API) based on a determination that the instruction is invalid; or   send a control signal to the hardware accelerator to cause the hardware accelerator to enter a low power state based on a determination that the instruction is invalid.   
     
     
         13 . The at least one non-transitory computer-readable medium of  claim 9 , the instructions, when executed further cause the security broker to:
 determine whether the hardware accelerator has responded to a Peripheral Component Interconnect Express (PCIe) request from the privileged component;   generate a response to the PCIe request from the privileged component on behalf of the hardware accelerator based on a determination that the hardware accelerator has not responded to the PCIe request from the privileged component; and   transmit the response to the privileged component.   
     
     
         14 . The at least one non-transitory computer-readable medium of  claim 9 , the instructions, when executed further cause the security broker to restrict the hardware accelerator from initiating Peripheral Component Interconnect Express (PCIe) transactions with the privileged component. 
     
     
         15 . A system, comprising:
 a hardware accelerator; and   circuitry coupled to the hardware accelerator, the circuitry to:
 determine whether an instruction received from the hardware accelerator is invalid, the instruction comprising an indication of a privileged component; and 
 apply a restriction to the instruction based on a determination that the instruction is invalid. 
   
     
     
         16 . The system of  claim 15 , the circuitry to determine whether the instruction is invalid based on at least one of:
 a protocol validation operation;   a network address permission check;   a memory address range permission check;   an amount of bandwidth used by the hardware accelerator;   an amount of thermal energy generated by the hardware accelerator; or   an amount of power used by the hardware accelerator.   
     
     
         17 . The system of  claim 15 , the circuitry to forward the instruction to the privileged component based on a determination that the instruction is valid. 
     
     
         18 . The system of  claim 15 , the circuitry to, at least one of the following:
 send a control signal to the hardware accelerator to cause the hardware accelerator to reset based on a determination that the instruction is invalid;   create an entry in a system log based on a determination that the instruction is invalid, the entry comprising an indication of the instruction;   generate and transmit a notification based on a determination that the instruction is invalid, the notification comprising an indication of the instruction;   report the instruction via an application programming interface (API) based on a determination that the instruction is invalid; or   send a control signal to the hardware accelerator to cause the hardware accelerator to enter a low power state based on a determination that the instruction is invalid.   
     
     
         19 . The system of  claim 15 , comprising an interface to couple to the privileged component. 
     
     
         20 . The system of  claim 1 , the circuitry to:
 determine whether the hardware accelerator has responded to a Peripheral Component Interconnect Express (PCIe) request from the privileged component;   generate a response to the PCIe request from the privileged component on behalf of the hardware accelerator based on a determination that the hardware accelerator has not responded to the PCIe request from the privileged component; and   transmit the response to the privileged component.   
     
     
         21 . The system of  claim 1 , the hardware accelerator comprising an FPGA-based accelerator, the FPGA-based accelerator disposed on a first die, the circuitry implemented as one of: a chiplet, a second FPGA on a second die, the second FPGA on the first die and decoupled from the FPGA-based accelerator, an application specific integrated circuit (ASIC) separate from the FPGA-based accelerator, or a baseboard management controller (BMC). 
     
     
         22 . A system, comprising:
 a privileged component; and   circuitry coupled to the privileged component, the circuitry to:
 determine whether an instruction received from a hardware accelerator is invalid, the instruction comprising an indication of the privileged component; and 
 apply a restriction to the instruction based on a determination that the instruction is invalid. 
   
     
     
         23 . The system of  claim 22 , the circuitry to forward the instruction to the privileged component based on a determination that the instruction is valid. 
     
     
         24 . The system of  claim 22 , the circuitry to, at least one of the following:
 send a control signal to the hardware accelerator to cause the hardware accelerator to reset based on a determination that the instruction is invalid;   create an entry in a system log based on a determination that the instruction is invalid, the entry comprising an indication of the instruction;   generate and transmit a notification based on a determination that the instruction is invalid, the notification comprising an indication of the instruction;   report the instruction via an application programming interface (API) based on a determination that the instruction is invalid; or   send a control signal to the hardware accelerator to cause the hardware accelerator to enter a low power state based on a determination that the instruction is invalid.   
     
     
         25 . The system of  claim 22 , the privileged component comprising one or more of: a processor, memory, a network interface, a graphics processor, or a Peripheral Component Interconnect Express (PCIe) device.