Storage device and method of operating the same

Abstract

In a storage device for controlling operational performance depending on temperature, a memory controller configured to control a memory device may include a flash translation layer block configured to receive data from a host and to convert a logic address into a physical address to store address information, during a write operation; a buffer memory configured to include a first buffer and a second buffer; an internal temperature sensing unit configured to generate an internal temperature information by sensing a temperature of the memory controller; and a performance adjustment unit configured to receive external temperature information from an external temperature sensing unit, and to control the flash translation layer block to store data in only one of the first or second buffer in a fast write mode based on the internal temperature information and the external temperature information, wherein the external temperature information represents a temperature of the memory device.

What is claimed is: 
     
         1 . A memory controller for controlling a memory device, the memory controller comprising:
 a flash translation layer block configured to receive data from a host and to convert a logic address into a physical address to store address information, during a write operation;   a buffer memory configured to include a first buffer and a second buffer;   an internal temperature sensing unit configured to generate an internal temperature information by sensing a temperature of the memory controller; and   a performance adjustment unit configured to receive an external temperature information from an external temperature sensing unit, and to control the flash translation layer block to store data in only one of the first and second buffer in a fast write mode based on the internal temperature information and the external temperature information,   wherein the external temperature information represents a temperature of the memory device.   
     
     
         2 . The memory controller according to  claim 1 , wherein the flash translation layer block updates mapping information on the data stored in the one of the first and second buffer after the fast write mode is terminated. 
     
     
         3 . The memory controller according to  claim 1 , wherein the performance adjustment unit controls data input/output speed of the memory controller based on the internal temperature information and the external temperature information. 
     
     
         4 . The memory controller according to  claim 1 , wherein the performance adjustment unit comprises:
 a correction value generation unit configured to generate a correction value based on the internal and external temperature information;   a performance adjustment determination unit configured to generate an adjusted temperature information, in which the correction value is applied to the internal temperature information, to compare the adjusted temperature information with pre-stored critical temperature information and then to determine whether to adjust an operational performance of the memory controller based on a result of the comparing; and   a correction value update control unit configured to generate an update enable signal for updating the correction value, and to output the update enable signal when a number of erase-write cycles (EW cycles) of the memory device exceeds a threshold number.   
     
     
         5 . The memory controller according to  claim 4 , wherein the performance adjustment determination unit controls the operational performance by outputting a throttling signal for activating a throttling operation that adjusts the operational performance of the memory controller when a write request for the memory device is inputted and the adjusted temperature information is higher than the critical temperature information. 
     
     
         6 . The memory controller according to  claim 5 , wherein the throttling operation is an operation of decreasing a data input/output speed of the memory controller. 
     
     
         7 . The memory controller according to  claim 5 , wherein the throttling operation is an operation of storing the data in only one of the first and second buffer in a fast write mode. 
     
     
         8 . The memory controller according to  claim 5 , wherein the throttling operation is an operation of storing the data in both the first and second buffer in a normal write mode. 
     
     
         9 . The memory controller according to  claim 5 , wherein, when the fast write mode is changed to a normal write mode, the flash translation layer block updates mapping information skipped in the fast write mode. 
     
     
         10 . The memory controller according to  claim 2 , wherein the flash translation layer block stores the data in the first and second buffers in a normal write mode during the write operation, and then invalidates data corresponding to a duplicated address by searching for a converted address for the data stored in the first and second buffers to update the mapping information. 
     
     
         11 . The memory controller according to  claim 5 , wherein:
 the memory controller is capable of simultaneously accessing a plurality of memory devices, and   the throttling operation is an operation of decreasing a number of memory devices that the memory controller simultaneously accesses.   
     
     
         12 . A storage device comprising:
 a plurality of memory devices;   an external temperature sensing unit configured to generate an external temperature information by sensing a temperature of the respective memory device; and   a buffer memory configured to include a first buffer and a second buffer;   a memory controller configured to:   control the plurality of memory devices,   receive data from a host,   convert a logic address into a physical address to store address information, during a write operation, and   control the buffer memory to store data in only one of the first and second buffer in a fast write mode based on internal temperature information and the external temperature information   wherein the internal temperature information represents a temperature of the memory controller.   
     
     
         13 . The storage device according to  claim 12 , wherein the memory controller controls data input/output speed of the memory controller using the internal temperature information and the external temperature information. 
     
     
         14 . The storage device according to  claim 12 , wherein the memory controller updates mapping information on the data stored in the one of the first and second buffer after the fast write mode is terminated. 
     
     
         15 . The storage device according to  claim 12 , wherein the memory controller updates mapping information on the data stored in the one of the first and second buffer after the fast write mode is changed to a normal write mode. 
     
     
         16 . The storage device according to  claim 12 , wherein the memory controller stores the data in the first and second buffers in a normal write mode during the write operation, and then invalidates data corresponding to a duplicated address by searching for a converted address for the data stored in the first and second buffers to update mapping information. 
     
     
         17 . The storage device according to  claim 12 , wherein the memory controller includes:
 a correction value generation unit configured to generate a correction value based on the internal and external temperature information;   a performance adjustment determination unit configured to generate an adjusted temperature information, in which the correction value is applied to the internal temperature information, to compare the adjusted temperature information with pre-stored critical temperature information and then to determine whether to adjust an operational performance of the memory controller based on a result of the comparing; and   a correction value update control unit configured to generate an update enable signal for updating the correction value, and to output the update enable signal when a number of erase-write cycles (EW cycles) of the memory device exceeds a threshold number.   
     
     
         18 . The storage device according to  claim 17 , wherein:
 the memory controller is capable of simultaneously accessing a plurality of memory devices, and   the performance adjustment determination unit is configured to adjust the operational performance by performing a throttling operation to decrease a number of memory devices that the memory controller simultaneously accesses.