Variable resistance memory device and method of manufacturing the same

Abstract

A variable resistance memory device and a method of manufacturing the same, the variable resistance memory device including a substrate including a first memory region and a second memory region; a plurality of first memory cells on the first memory region; and a plurality of second memory cells on the second memory region, wherein each of the first memory cells includes a first resistance element and a selection element, each of the second memory cells includes a second resistance element, and a maximum value of a variable resistance of the second resistance element is less than a maximum value of a variable resistance of the first resistance element.

What is claimed is: 
     
         1 . A variable resistance memory device, comprising:
 a substrate including a first memory region and a second memory region;   a plurality of first memory cells on the first memory region; and   a plurality of second memory cells on the second memory region,   wherein:   each of the first memory cells includes a first resistance element and a selection element,   each of the second memory cells includes a second resistance element, and   a maximum value of a variable resistance of the second resistance element is less than a maximum value of a variable resistance of the first resistance element.   
     
     
         2 . The variable resistance memory device as claimed in  claim 1 , further comprising:
 a first conductive line electrically connected to each of the first memory cells and between each of the first memory cells and the substrate;   a second conductive line electrically connected to the first memory cells and on the first memory cells; and   a transistor electrically connected to each of the second memory cells, the transistor being in the substrate,   wherein:   the first conductive line extends in a first direction parallel to a top surface of the substrate, and   the second conductive line extends in a second direction parallel to the top surface of the substrate and perpendicular to the first direction.   
     
     
         3 . The variable resistance memory device as claimed in  claim 1 , wherein:
 the first resistance element includes a first bottom electrode, a first top electrode on the first bottom electrode, and a first variable resistance pattern between the first bottom electrode and the first top electrode,   the second resistance element includes a second bottom electrode, a second top electrode on the second bottom electrode, and a second variable resistance pattern disposed between the second bottom electrode and the second top electrode, and   a level of a top surface of the first top electrode is substantially the same as a level of a top surface of the second top electrode.   
     
     
         4 . The variable resistance memory device as claimed in  claim 3 , wherein a level of a top surface of the first bottom electrode is substantially the same as a level of a top surface of the second bottom electrode. 
     
     
         5 . The variable resistance memory device as claimed in  claim 3 , wherein:
 each of the first variable resistance pattern and the second variable resistance pattern independently include a metal oxide; and   the first variable resistance pattern and the second variable resistance pattern include different materials from each other.   
     
     
         6 . The variable resistance memory device as claimed in  claim 3 , wherein a level of a bottom surface of the first bottom electrode is higher than a level of a bottom surface of the second bottom electrode. 
     
     
         7 . The variable resistance memory device as claimed in  claim 1 , wherein a thickness of the first resistance element in a third direction perpendicular to a top surface of the substrate is less than a thickness of the second resistance element in the third direction. 
     
     
         8 . The variable resistance memory device as claimed in  claim 1 , further comprising:
 a first sub-bottom electrode between the first resistance element and the substrate; and   a second sub-bottom electrode between the second resistance element and the substrate,   wherein the first sub-bottom electrode, the selection element, and the first resistance element are sequentially stacked in the first memory cell.   
     
     
         9 . The variable resistance memory device as claimed in  claim 8 , wherein a level of a top surface of the first sub-bottom electrode is substantially the same as a level of a top surface of the second sub-bottom electrode. 
     
     
         10 . The variable resistance memory device as claimed in  claim 1 , wherein the selection element includes a PN diode, an ovonic threshold switch (OTS) element, or a mixed ionic electronic conductor (MIEC). 
     
     
         11 . A method of manufacturing a variable resistance memory device, the method comprising:
 forming a bottom electrode material layer on a substrate that includes a first memory region and a second memory region;   forming a first variable resistance material layer on the bottom electrode material layer;   forming a first top electrode material layer on the first variable resistance material layer;   removing the first variable resistance material layer and the first top electrode material layer on the second memory region;   forming a second variable resistance material layer on the substrate;   forming a second top electrode material layer on the second variable resistance material layer;   removing the second variable resistance material layer and the second top electrode material layer on the first memory region; and   patterning the bottom electrode material layer, the first variable resistance material layer, the second variable resistance material layer and the first and second top electrode material layers, which remain on the substrate, to form first memory cells on the first memory region and second memory cells on the second memory region,   wherein:   removing the second variable resistance material layer and the second top electrode material layer on the first memory region includes performing a planarization process to expose the first top electrode material layer on the first memory region, and   the first variable resistance material layer includes a material of which a maximum resistance value is different from that of a material of the second variable resistance material layer.   
     
     
         12 . The method as claimed in  claim 11 , wherein the planarization process is performed until a level of a top surface of the first top electrode material layer on the first memory region is substantially the same as a level of a top surface of the second top electrode material layer on the second memory region. 
     
     
         13 . The method as claimed in  claim 11 , wherein each of the first memory cells and the second memory cells is electrically connected to a transistor in the substrate. 
     
     
         14 . The method as claimed in  claim 11 , further comprising forming a selection element material layer on the substrate such that the selection element material layer is between the bottom electrode material layer and the substrate. 
     
     
         15 . The method as claimed in  claim 11 , wherein forming the first variable resistance material layer and forming the second variable resistance material layer independently include performing an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or a co-sputtering process. 
     
     
         16 . The method as claimed in  claim 11 , further comprising forming a selection element material layer on one of the first memory region and the second memory region such that wherein the selection element material layer is between the bottom electrode material layer and the substrate. 
     
     
         17 . The method as claimed in  claim 11 , wherein each of the first variable resistance material layer and the second variable resistance material layer includes an oxide including Ti, Zr, Al, Hf, or Si. 
     
     
         18 . The method as claimed in  claim 11 , further comprising:
 forming a first conductive line electrically connected to each of the first memory cells, the first conductive line being on the first memory region and between each of the first memory cells and the substrate; and   forming a second conductive line electrically connected to the first memory cells, the second conductive line being on the first memory cells,   wherein:   the second memory region includes a transistor electrically connected to each of the second memory cells,   the first conductive line extends in a first direction parallel to a top surface of the substrate, and   the second conductive line extends in a second direction parallel to the top surface of the substrate and perpendicular to the first direction.   
     
     
         19 . The method as claimed in  claim 11 , wherein the planarization process includes a chemical mechanical polishing (CMP) process. 
     
     
         20 . The method as claimed in  claim 11 , further comprising forming a sub-bottom electrode material layer on the substrate.