Fabrication of correlated electron material (cem) devices

Abstract

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments a method may include forming a structure on a first portion of a substrate while maintaining a second portion of the substrate exposed. A sealing layer may be deposited over the structure and over at least a portion of the exposed second portion of the substrate. A conductive via may be formed by way of a dry etch through the sealing layer to contact the exposed metal layer. In embodiments, an etch-stop control layer may be utilized to control an etching process prior to formation of metal contacts over the CEM switch and the conductive via.

What is claimed is: 
     
         1 .- 14 . (canceled) 
     
     
         15 . A method comprising:
 forming an etch-stop control layer over a device;   forming a first layer of insulative filling material over the etch-stop control layer;   initiating a process to remove a localized portion of the first layer of insulative material; and   altering the process to etch the localized portion responsive to detection of removal of at least a portion of the etch-stop control layer.   
     
     
         16 . The method of  claim 15 , wherein the device further comprises a conductive overlay layer, the method further comprising, prior to the forming of the etch-stop control layer:
 removing a portion of a second layer of insulative filling material disposed over the conductive overlay layer to reveal a top surface of the conductive overlay that is coplanar with a top surface of a remaining portion of the second layer of insulative filling material adjacent to the device,   wherein the etch-stop control layer is formed over the top surface of the conductive overlay and the remaining portion of the second layer of insulative material.   
     
     
         17 . The method of  claim 16 , wherein removing the portion of the second layer of the insulative filing material disposed over the conductive overlay layer to reveal the top surface of the conductive overlay comprises chemical mechanical polishing to planarize the top surface of the conductive overlay and the top surface of the remaining portion of the first layer of insulative material. 
     
     
         18 . The method of  claim 15 , wherein the etch-stop control layer is formed over a conductive overlay, and the method further comprises:
 continuing the altered process to etch the localized portion until at least a portion of the conductive overlay is revealed.   
     
     
         19 . The method of  claim 15 , wherein the insulative filling material comprises an insulative filling material having a relative dielectric constant of between about 2.0 and about 4.5. 
     
     
         20 . (canceled) 
     
     
         21 . The method of  claim 15 , wherein the etch-stop control layer comprises an atomic or molecular concentration of at least 50.0% silicon nitride or aluminum nitride, or combination thereof. 
     
     
         22 . The method of  claim 15 , further comprising terminating the etching responsive to sensing one or more gaseous components of the etch-stop control layer in a chamber. 
     
     
         23 . The method of  claim 15 , wherein the etch-stop control layer comprises a thickness of between about 1.0 nm and about 50.0 nm. 
     
     
         24 . The method of  claim 15 , further comprising depositing a metal on the conductive overlay following the terminating of the etching of the localized portion. 
     
     
         25 . The method of  claim 15 ,
 wherein the first layer of insulative filling material comprises a thickness of between about 5.0 nm to about 20.0 nm.   
     
     
         26 . The method of  claim 15 , further comprising depositing a hardmask over the first layer of insulative filling material prior to removal of the at least a portion of the first layer of insulative filling material. 
     
     
         27 . The method of  claim 26 , wherein the altering the process to remove the at least the portion of the first layer of the insulative filling material occurs responsive to detecting one or more gaseous components of the etch-stop control layer in a chamber. 
     
     
         28 .- 31 . (canceled) 
     
     
         32 . The method of  claim 15 , wherein the device comprises a conductive film disposed over a first portion of a substrate and a correlated electron material (CEM) film disposed over the conductive film, and wherein the method further comprises:
 forming a sealing layer over the device and at least a second portion of the substrate;   forming a second layer of insulative filling material over at least a portion of the sealing layer deposited over the second portion of the substrate; and   removing a portion of the second layer of insulative filling material prior to removal of the at least a portion of the sealing layer disposed over the second portion of the substrate.   
     
     
         33 . The method of  claim 32 , further comprising forming a metal via filling the removed portion of the sealing layer to extend from an exposed metal layer to a metal layer disposed under the substrate. 
     
     
         34 . The method of  claim 32 , wherein the removing of the portion of the sealing layer to expose the metal layer comprises performing a dry etch to remove the portion of the sealing layer. 
     
     
         35 . The method of  claim 34 , wherein the dry etch comprises reactive ion etching or plasma sputter etching, or a combination thereof. 
     
     
         36 . The method of  claim 32 , wherein the portion of the second layer of insulative filling material and the at least a portion of the sealing layer disposed over the second portion of the substrate are removed in a single etch process step to form a trench, and the method further comprises:
 depositing a metal in the trench to form a metal via extending from an exposed metal layer to a metal layer disposed under the substrate.   
     
     
         37 . The method of  claim 32 , wherein the sealing layer comprises an atomic or molecular concentration of at least 50.0% silicon nitride, silicon carbide or silicon carbon nitride, or any combination thereof. 
     
     
         38 . The method of  claim 32 , wherein the sealing layer comprises a thickness of between about 2.0 nm and about 100.0 nm. 
     
     
         39 . The method of  claim 32 , and further comprising:
 forming the conductive film over a metal layer;   forming one or more layers of CEM on the conductive film to form the CEM film;   forming a conductive overlay over the CEM film; and   removing a portion of the one or more layers of CEM, a portion of the conductive overlay and a portion of the conductive film to expose the second portion of the substrate,   wherein the sealing layer is formed over the exposed second portion of the substrate.