US2020295199A1PendingUtilityA1

Liquid crystal display device and electronic device including the same

Assignee: SEMICONDUCTOR ENERGY LABPriority: Oct 21, 2009Filed: May 29, 2020Published: Sep 17, 2020
Est. expiryOct 21, 2029(~3.2 yrs left)· nominal 20-yr term from priority
H10D 30/6755H10D 30/6706H10D 86/60G09G 2300/0439G09G 2300/0426G02F 2201/40G09G 3/36G02F 1/13624G02F 1/136213G02F 1/1368H10D 86/481H10D 86/441H10D 86/423H10D 86/0221H10D 62/80H10D 30/6757H10D 30/6739G02F 1/134345G09G 3/3677G09G 3/3614G02F 2201/123G02F 1/13439G09G 3/3648G02F 1/136286G09G 2300/0465G02F 1/134336G02F 1/133345H01L 29/4908H01L 27/127H01L 29/24H01L 29/78609H01L 27/1255H01L 27/1225G02F 2001/134345H01L 29/7869H01L 29/78696H01L 27/124
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Claims

Abstract

A liquid crystal display device is provided in which the aperture ratio can be increased in a pixel including a thin film transistor in which an oxide semiconductor is used. In the liquid crystal display device, the thin film transistor including a gate electrode, a gate insulating layer and an oxide semiconductor layer which are provided so as to overlap with the gate electrode, and a source electrode and a drain electrode which overlap part of the oxide semiconductor layer is provided between a signal line and a pixel electrode which are provided in a pixel portion. The off-current of the thin film transistor is 1×1013 A or less. A potential can be held only by a liquid crystal capacitor, without a capacitor which is parallel to a liquid crystal element, and a capacitor connected to the pixel electrode is not formed in the pixel portion.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first conductive layer comprising a region serving as one electrode of a capacitor;   a second conductive layer comprising a region serving as a gate electrode;   an oxide semiconductor layer comprising a region overlapping with the gate electrode with a gate insulating layer therebetween;   a third conductive layer electrically connected to the oxide semiconductor layer and comprising a region serving as one of a source electrode and a drain electrode;   an oxide insulating layer over the first conductive layer, the second conductive layer, the third conductive layer, and the oxide semiconductor layer, the oxide insulating layer comprising a region in contact with a top surface of the oxide semiconductor layer; and   a pixel electrode electrically connected to the third conductive layer through an opening portion of the oxide insulating layer,   wherein a hydrogen concentration in the oxide semiconductor layer is 5×10 19 /cm 3  or less,   wherein the first conductive layer comprises the same material as the second conductive layer,   wherein the opening portion and the first conductive layer overlap each other in a top view of the semiconductor device, and   wherein a region where the pixel electrode and the third conductive layer overlap each other entirely overlaps with the first conductive layer in the top view of the semiconductor device.   
     
     
         3 . A semiconductor device according to  claim 2 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 
     
     
         4 . A semiconductor device according to  claim 2 , wherein a width of the oxide semiconductor layer is larger than a width of the second conductive layer in a cross-sectional view in a channel length direction of a transistor comprising the oxide semiconductor layer. 
     
     
         5 . A semiconductor device according to  claim 2 , wherein each of the first conductive layer and the second conductive layer comprises copper. 
     
     
         6 . A semiconductor device according to  claim 2 , wherein the semiconductor device is a liquid crystal display device. 
     
     
         7 . A semiconductor device comprising:
 a first conductive layer comprising a region serving as one electrode of a capacitor;   a second conductive layer comprising a region serving as a gate electrode;   an oxide semiconductor layer comprising a region overlapping with the gate electrode with a gate insulating layer therebetween;   a third conductive layer electrically connected to the oxide semiconductor layer and comprising a region serving as one of a source electrode and a drain electrode;   an oxide insulating layer over the first conductive layer, the second conductive layer, the third conductive layer, and the oxide semiconductor layer, the oxide insulating layer comprising a region in contact with a top surface of the oxide semiconductor layer; and   a pixel electrode electrically connected to the third conductive layer through an opening portion of the oxide insulating layer,   wherein the first conductive layer comprises the same material as the second conductive layer,   wherein the opening portion and the first conductive layer overlap each other in a top view of the semiconductor device, and   wherein a region where the pixel electrode and the third conductive layer overlap each other entirely overlaps with the first conductive layer in the top view of the semiconductor device.   
     
     
         8 . A semiconductor device according to  claim 7 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 
     
     
         9 . A semiconductor device according to  claim 7 , wherein a width of the oxide semiconductor layer is larger than a width of the second conductive layer in a cross-sectional view in a channel length direction of a transistor comprising the oxide semiconductor layer. 
     
     
         10 . A semiconductor device according to  claim 7 , wherein each of the first conductive layer and the second conductive layer comprises copper. 
     
     
         11 . A semiconductor device according to  claim 7 , wherein the semiconductor device is a liquid crystal display device. 
     
     
         12 . A semiconductor device comprising:
 a first conductive layer comprising a region serving as one electrode of a capacitor;   a second conductive layer comprising a region serving as a gate electrode;   an oxide semiconductor layer comprising a region overlapping with the gate electrode with a gate insulating layer therebetween;   a third conductive layer electrically connected to the oxide semiconductor layer and comprising a region serving as one of a source electrode and a drain electrode;   a fourth conductive layer comprising a region serving the other of the source electrode and the drain electrode;   an oxide insulating layer over the first conductive layer, the second conductive layer, the third conductive layer, and the oxide semiconductor layer, the oxide insulating layer comprising a region in contact with a top surface of the oxide semiconductor layer; and   a pixel electrode electrically connected to the third conductive layer through an opening portion of the oxide insulating layer,   wherein the first conductive layer comprises the same material as the second conductive layer,   wherein the first conductive layer comprises a region overlapping with the fourth conductive layer in a top view of the semiconductor device,   wherein the opening portion and the first conductive layer overlap each other in the top view of the semiconductor device, and   wherein a region where the pixel electrode and the third conductive layer overlap each other entirely overlaps with the first conductive layer in the top view of the semiconductor device.   
     
     
         13 . A semiconductor device according to  claim 12 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 
     
     
         14 . A semiconductor device according to  claim 12 , wherein a width of the oxide semiconductor layer is larger than a width of the second conductive layer in a cross-sectional view in a channel length direction of a transistor comprising the oxide semiconductor layer. 
     
     
         15 . A semiconductor device according to  claim 12 , wherein each of the first conductive layer and the second conductive layer comprises copper. 
     
     
         16 . A semiconductor device according to  claim 12 , wherein the semiconductor device is a liquid crystal display device.

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