Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same

Abstract

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

What is claimed is: 
     
         1 . A semiconductor chip, comprising:
 a first conductive structure forming both a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, the first conductive structure having a linear shape extending between a first end of the first conductive structure and a second end of the first conductive structure;   a second conductive structure forming a gate electrode of a second transistor of the first transistor type;   a third conductive structure forming a gate electrode of a second transistor of the second transistor type, the third conductive structure having a linear shape extending between a first end of the third conductive structure and a second end of the third conductive structure, the first end of the third conductive structure substantially aligned with the first end of the first conductive structure, the second end of the third conductive structure substantially aligned with the second end of the first conductive structure;   a first diffusion region of a first diffusion type forming part of both the first and second transistors of the first transistor type;   a first diffusion region of a second diffusion type forming part of both the first and second transistors of the second transistor type; and   a common node electrical connection extending from the first diffusion region of the first diffusion type to the first diffusion region of the second diffusion type.   
     
     
         2 . The semiconductor chip as recited in  claim 1 , wherein the first diffusion region of the first diffusion type is physically separated from the first diffusion region of the second diffusion type. 
     
     
         3 . The semiconductor chip as recited in  claim 1 , wherein the common node electrical connection includes a first contact structure contacting the first diffusion region of the first diffusion type, a second contact structure contacting the first diffusion region of the second diffusion type, and an interconnect level conductive structure contacting both the first contact structure and the second contact structure. 
     
     
         4 . The semiconductor chip as recited in  claim 3 , wherein the interconnect level conductive structure has a linear shape. 
     
     
         5 . The semiconductor chip as recited in  claim 4 , further comprising:
 a second diffusion region of the first diffusion type forming part of the first transistor of the first transistor type;   a second diffusion region of the second diffusion type forming part of the second transistor of the second transistor type; and   a first electrical connection extending from the second diffusion region of the first diffusion type to the second diffusion region of the second diffusion type.   
     
     
         6 . The semiconductor chip as recited in  claim 5 , wherein the first electrical connection includes a third contact structure contacting the second diffusion region of the first diffusion type, a fourth contact structure contacting the second diffusion region of the second diffusion type, and a plurality of interconnect level conductive structures, wherein one of the plurality of interconnect level conductive structures contacts the third contact structure and another of the plurality of interconnect level conductive structures contacts the fourth contact structure. 
     
     
         7 . The semiconductor chip as recited in  claim 6 , wherein the plurality of interconnect level conductive structures includes at least two interconnect level conductive structures in a first interconnect level and at least one interconnect level conductive structure in a second interconnect level, and wherein the first electrical connection includes both a first via conductive structure and a second via conductive structure connected to the at least one interconnected level conductive structure in the second interconnect level, the first via conductive structure also connected to a first of the at least two interconnect level conductive structures in the first interconnect level, the second via conductive structure also connected to a second of the at least two interconnect level conductive structures in the first interconnect level. 
     
     
         8 . The semiconductor chip as recited in  claim 7 , wherein the at least one interconnect level conductive structure in the second interconnect level crosses over both the first conductive structure and the interconnect level conductive structure of the common node electrical connection. 
     
     
         9 . The semiconductor chip as recited in  claim 6 , further comprising:
 a third diffusion region of the first diffusion type forming part of the second transistor of the first transistor type;   a third diffusion region of the second diffusion type forming part of the first transistor of the second transistor type; and   a second electrical connection extending from the third diffusion region of the first diffusion type to the third diffusion region of the second diffusion type.   
     
     
         10 . The semiconductor chip as recited in  claim 9 , wherein the second electrical connection includes a fifth contact structure contacting the third diffusion region of the first diffusion type, a sixth contact structure contacting the third diffusion region of the second diffusion type, and a second plurality of interconnect level conductive structures, wherein one of the second plurality of interconnect level conductive structures contacts the fifth contact structure and another of the second plurality of interconnect level conductive structures contacts the sixth contact structure. 
     
     
         11 . The semiconductor chip as recited in  claim 10 , wherein the second plurality of interconnect level conductive structures includes at least two interconnect level conductive structures in the first interconnect level and at least one interconnect level conductive structure in the second interconnect level, and wherein the second electrical connection includes both a first via conductive structure and a second via conductive structure connected to the at least one interconnected level conductive structure in the second interconnect level, the first via conductive structure also connected to a first of the at least two interconnect level conductive structures in the first interconnect level, the second via conductive structure also connected to a second of the at least two interconnect level conductive structures in the first interconnect level. 
     
     
         12 . The semiconductor chip as recited in  claim 1 , wherein the second conductive structure has a linear shape extending between a first end of the second conductive structure and a second end of the second conductive structure. 
     
     
         13 . The semiconductor chip as recited in  claim 1 , wherein the first end of the second conductive structure is substantially aligned with both the first end of the first conductive structure and the first end of the third conductive structure. 
     
     
         14 . The semiconductor chip as recited in  claim 13 , wherein the second end of the second conductive structure is not aligned with second end of the first conductive structure, and the second end of the second conductive structure is not aligned with the second end of the third conductive structure. 
     
     
         15 . The semiconductor chip as recited in  claim 13 , wherein a length of the second conductive structure as measured between the first and second ends of the second conductive structure is less than one-half of a length of the first conductive structure as measured between the first and second ends of the first conductive structure, and wherein the length of the second conductive structure as measured between the first and second ends of the third conductive structure is less than one-half of a length of the third conductive structure as measured between the first and second ends of the third conductive structure. 
     
     
         16 . The semiconductor chip as recited in  claim 1 , wherein the first diffusion region of the first diffusion type is physically separated from the first diffusion region of the second diffusion type by an inner region that does not include a diffusion region, wherein the first conductive structure includes an outer portion that extends away from both the gate electrode of the first transistor of the second transistor type and the inner region. 
     
     
         17 . The semiconductor chip as recited in  claim 16 , further comprising:
 a gate contact structure contacting the outer portion of the first conductive structure.   
     
     
         18 . The semiconductor chip as recited in  claim 1 , wherein the first diffusion region of the first diffusion type is physically separated from the first diffusion region of the second diffusion type by an inner region that does not include a diffusion region, wherein the second conductive structure includes an outer portion that extends away from both the gate electrode of the second transistor of the first transistor type and the inner region. 
     
     
         19 . The semiconductor chip as recited in  claim 18 , further comprising:
 a first gate contact structure contacting the outer portion of the second conductive structure.   
     
     
         20 . The semiconductor chip as recited in  claim 19 , further comprising:
 a second gate contact structure contacting the third conductive structure; and   a linear-shaped interconnect level conductive structure contacting both the first gate contact structure and the second gate contact structure.