Memory device

Abstract

A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

What is claimed is: 
     
         1 . A memory system comprising:
 a plurality of memory devices; and   a power management integrated circuit (PMIC) configured to manage a power source applied to the plurality of memory devices in response to a power control signal and an input power source, and coupled to a battery module.   
     
     
         2 . The memory system according to  claim 1 , wherein the power management integrated circuit (PMIC) selectively controls a voltage mode in response to voltage and battery information received from the battery module. 
     
     
         3 . The memory system according to  claim 1 , wherein the power management integrated circuit (PMIC) receives residual storage capacity information of the battery module. 
     
     
         4 . The memory system according to  claim 1 , wherein the power management integrated circuit (PMIC) includes:
 a voltage generator configured to generate a plurality of internal voltages;   a temperature sensor configured to sense temperature information;   a storage circuit configured to store the temperature information and voltage information of the voltage generator; and   a power controller configured to control a voltage mode in response to information stored in the storage circuit.   
     
     
         5 . The memory system according to  claim 4 , wherein the voltage generator includes at least one of a Low Drop-Out (LD 0 ) regulator providing a low voltage, and a switching regulator. 
     
     
         6 . The memory system according to  claim 1 , wherein the power management integrated circuit (PMIC) selectively operates a plurality of regulators in response to the power control signal. 
     
     
         7 . The memory system according to  claim 1 , wherein the power management integrated circuit (PMIC) further includes:
 a serial presence detect (SPD) circuit configured to store information and temperature information of the plurality of memory devices; and   a register clock driver (RCD) configured to drive a clock signal, and provide the clock signal to the plurality of memory devices.   
     
     
         8 . A memory system comprising:
 a memory module configured to include a plurality of memory devices and a controller controlling the plurality of memory devices;   a power management integrated circuit (PMIC) configured to manage a power source applied to the plurality of memory devices in response to a power control signal and an input power source; and   a memory controller configured to control operations of the memory module, and generate the power control signal in response to residual storage capacity information of a battery module.   
     
     
         9 . The memory system according to  claim 8 , wherein the power management integrated circuit (PMIC) is contained in the memory module. 
     
     
         10 . The memory system according to  claim 8 , wherein the memory controller determines priority information of data to be communicated between the plurality of memory devices in response to the residual storage capacity information. 
     
     
         11 . The memory system according to  claim 8 , wherein:
 when a residual storage capacity of the battery module is less than a reference storage capacity, the memory controller primarily transmits higher-priority data having higher importance.   
     
     
         12 . The memory system according to  claim 11 , wherein the higher-priority data having higher importance is established in order of metadata→map data→user data. 
     
     
         13 . A memory system comprising:
 a memory module configured to include a plurality of memory devices and a controller controlling the plurality of memory devices;   a power management integrated circuit (PMIC) configured to manage a power source applied to the plurality of memory devices in response to a power control signal and an input power source;   a memory controller configured to control operations of the memory module, and generate the power control signal; and   a register contained in each of the memory module, the power management integrated circuit (PMIC), and the memory controller, and configured to store characteristic information of the plurality of memory devices.   
     
     
         14 . The memory system according to  claim 13 , wherein the characteristic information includes at least one of parameter information and operation mode information. 
     
     
         15 . The memory system according to  claim 13 , wherein the characteristic information includes at least one of a refresh operation parameter, a write operation parameter, and an asynchronous operation parameter. 
     
     
         16 . The memory system according to  claim 13 , wherein the register stores a power potential value predetermined by a test operation. 
     
     
         17 . The memory system according to  claim 16 , wherein the power management integrated circuit (PMIC) provides different power sources to the respective memory devices in response to the power potential value stored in the register. 
     
     
         18 . The memory system according to  claim 13 , wherein the power management integrated circuit (PMIC) changes setting information of a mode register set (MRS) in response to a power potential value stored in the register. 
     
     
         19 . The memory system according to  claim 13 , wherein the power management integrated circuit (PMIC) provides different power sources to the plurality of memory devices in response to temperature information stored in the register. 
     
     
         20 . The memory system according to  claim 13 , further comprising:
 a built-in self-test (BIST) circuit contained in each of the memory module, the power management integrated circuit (PMIC), and the memory controller, and configured to detect a power potential value for each memory device.   
     
     
         21 . The memory system according to  claim 20 , further comprising:
 a serial presence detect (SPD) circuit configured to store information detected by the built-in self-test (BIST) circuit.   
     
     
         22 . The memory system according to  claim 20 , wherein the built-in self-test (BIST) circuit performs a test operation in response to temperature information.