US2020287997A1PendingUtilityA1

Parameter encoding techniques for wireless communication networks

Assignee: INTEL IP CORPPriority: Apr 1, 2017Filed: Mar 18, 2020Published: Sep 10, 2020
Est. expiryApr 1, 2037(~10.7 yrs left)· nominal 20-yr term from priority
H04L 69/16H04W 28/0205H04L 69/323H04L 1/0083H04W 28/0252H04W 80/10
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Claims

Abstract

Parameter encoding techniques for wireless communication networks are described. In some embodiments, an apparatus may comprise a memory and logic for a wireless communication device, at least a portion of the logic comprised in circuitry coupled to the memory, the logic to determine a channel usage configuration to be applied for a transmission of a packet to a remote device, the channel usage configuration to designate a primary channel and one or more data transmission channels, generate a PHY header for the packet, the PHY header to comprise a first field comprising information indicating the one or more data transmission channels and a second field comprising information identifying the primary channel, and encode the PHY header for wireless transmission. Other embodiments are described and claimed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus, comprising:
 a memory; and   a processing circuit coupled to the memory, the logic to:
 generate a PHY header for the packet, the PHY header to comprise:
 a first field comprising information indicating the one or more data transmission channels, the first field to comprise a bitmap, the bitmap to comprise 8 bits, each bit of the 8 bits to correspond to a respective 2.16 gigahertz (GHz) channel; and 
 a second field comprising information identifying the primary channel, the second field to comprise a three-bit value to indicate the primary channel, wherein the three-bit value comprises an index value, the index value based on primary channel; and 
 
 encode the PHY header for wireless transmission. 
   
     
     
         2 . The apparatus of  claim 1 , the second field to comprise a three-bit value indicating which one of the 2.16 GHz channels constitutes the primary channel. 
     
     
         3 . The apparatus of  claim 1 , the PHY header to comprise a second field to comprise a three-bit value to indicate the primary channel. 
     
     
         4 . The apparatus of  claim 1 , the bitmap to describe a 2.16 GHz channel, a 4.32 GHz channel, a 6.48 GHz channel, or an 8.64 GHz channel. 
     
     
         5 . The apparatus of  claim 1 , the bitmap to describe a 2.16 GHz+2.16 GHz channel. 
     
     
         6 . The apparatus of  claim 1 , the processing circuit coupled with a radio interface, the radio interface comprising a transmitter and a receiver. 
     
     
         7 . The apparatus of  claim 6 , the radio interface coupled with at least one antenna. 
     
     
         8 . An apparatus, comprising:
 a memory; and   a processing circuit coupled to the memory, the logic to:
 decode a PHY header for the packet, the PHY header to comprise:
 a first field to comprise a bitmap, the bitmap to comprise 8 bits, each bit of the 8 bits to correspond to a respective 2.16 gigahertz (GHz) channel; and 
 a bit indicating whether aggregation of more than one channel is to be used for transmission of the packet or aggregation of more than one channel is not to be used. 
 
   
     
     
         9 . The apparatus of  claim 8 , the second field to comprise a three-bit value indicating which one of the 2.16 GHz channels constitutes the primary channel. 
     
     
         10 . The apparatus of  claim 8 , the PHY header to comprise a second field to comprise a three-bit value to indicate the primary channel. 
     
     
         11 . The apparatus of  claim 8 , the bitmap to describe a 2.16 GHz channel, a 4.32 GHz channel, a 6.48 GHz channel, or an 8.64 GHz channel. 
     
     
         12 . The apparatus of  claim 8 , the bitmap to describe a 2.16 GHz+2.16 GHz channel. 
     
     
         13 . The apparatus of  claim 8 , the processing circuit coupled with a radio interface, the radio interface comprising a transmitter and a receiver. 
     
     
         14 . The apparatus of  claim 13 , the radio interface coupled with at least one antenna. 
     
     
         15 . At least one non-transitory computer-readable storage medium comprising a set of instructions that, in response to being executed at a wireless communication device, cause the wireless communication device to:
 generate a PHY header for the packet, the PHY header to comprise:
 a first field to comprise a bitmap, the bitmap to comprise 8 bits, each bit of the 8 bits to correspond to a respective 2.16 gigahertz (GHz) channel; and 
 a bit indicating whether aggregation of more than one channel is to be used for transmission of the packet or aggregation of more than one channel is not to be used; and 
   encode the PHY header for wireless transmission.   
     
     
         16 . The at least one non-transitory computer-readable storage medium of  claim 15 , the second field to comprise a three-bit value indicating which one of the 2.16 GHz channels constitutes the primary channel. 
     
     
         17 . The at least one non-transitory computer-readable storage medium of  claim 15 , the PHY header to comprise a second field to comprise a three-bit value to indicate the primary channel. 
     
     
         18 . The at least one non-transitory computer-readable storage medium of  claim 15 , the bitmap to describe a 2.16 GHz channel, a 4.32 GHz channel, a 6.48 GHz channel, or an 8.64 GHz channel. 
     
     
         19 . The at least one non-transitory computer-readable storage medium of  claim 15 , the bitmap to describe a 2.16 GHz+2.16 GHz channel. 
     
     
         20 . At least one non-transitory computer-readable storage medium comprising a set of instructions that, in response to being executed at a wireless communication device, cause the wireless communication device to:
 decode a PHY header for the packet, the PHY header to comprise:
 a first field to comprise a bitmap, the bitmap to comprise 8 bits, each bit of the 8 bits to correspond to a respective 2.16 gigahertz (GHz) channel; and 
 a bit indicating whether aggregation of more than one channel is to be used for transmission of the packet or aggregation of more than one channel is not to be used. 
   
     
     
         21 . The at least one non-transitory computer-readable storage medium of  claim 20 , the second field to comprise a three-bit value indicating which one of the 2.16 GHz channels constitutes the primary channel. 
     
     
         22 . The at least one non-transitory computer-readable storage medium of  claim 20 , the PHY header to comprise a second field to comprise a three-bit value to indicate the primary channel. 
     
     
         23 . The at least one non-transitory computer-readable storage medium of  claim 20 , the bitmap to describe a 2.16 GHz channel, a 4.32 GHz channel, a 6.48 GHz channel, or an 8.64 GHz channel. 
     
     
         24 . The at least one non-transitory computer-readable storage medium of  claim 20 , the bitmap to describe a 2.16 GHz+2.16 GHz channel.

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