Pixel structure and display panel

Abstract

The present disclosure illustrates a pixel structure and a display panel. The pixel structure includes a plurality of data lines spaced apart from each other and electrically connected to a source driver; a plurality of scan lines spaced apart from each other and crossing the plurality of data lines, respectively, to form a plurality of pixel areas; at least one the connection line disposed in parallel with the plurality of data lines and electrically connected to the gate driver, and in each pixel at least one connection line is electrically connected to the scan line corresponding thereto.

What is claimed is: 
     
         1 . A pixel structure, comprising:
 a plurality of data lines spaced apart from each other, wherein the plurality of data lines are electrically connected to a source driver;   a plurality of scan lines spaced apart from each other, wherein the plurality of scan lines crossing the plurality of data lines, respectively, to form a plurality of pixel areas; and   at least one connection line disposed in parallel with the plurality of data lines and electrically connected to a gate driver, wherein in each of the plurality of pixel areas, the at least one connection line is electrically connected to at least one of the plurality of scan lines.   
     
     
         2 . The pixel structure according to  claim 1 , wherein the pixel structure comprises a plurality of active switches, and the plurality of connection lines are electrically connected to the plurality of scan lines respectively, in each of the plurality of pixel areas. 
     
     
         3 . A pixel structure, comprising:
 a plurality of data lines spaced apart from each other, wherein the plurality of data lines electrically connected to a source driver;   a plurality of scan lines spaced apart from each other, wherein the plurality of scan lines crossing the plurality of data lines, respectively, to form a plurality of pixel areas; and   a plurality of connection lines disposed in parallel with the plurality of data lines and electrically connected to a gate driver;   wherein the pixel structure comprises a plurality of active switches, and in each of the plurality of pixel areas, the plurality of connection lines are electrically connected to the plurality of scan lines, respectively;   wherein the pixel structure is formed on an active switch array substrate of a display panel.   
     
     
         4 . A display panel, comprising:
 an active switch array substrate;   an color filter substrate disposed opposite to the active switch array substrate; and   an liquid crystal layer formed between the active switch array substrate and the color filter substrate;   wherein the active switch array substrate comprises:
 a source driver disposed on the active switch array substrate; 
 a gate driver disposed on the active switch array substrate, wherein the source driver and the gate driver are disposed in the same direction on the active switch array substrate; 
 a plurality of data lines spaced apart from each other and electrically connected to the source driver; 
 a plurality of scan lines spaced apart from each other and crossing the plurality of data lines, respectively, to form a plurality of pixel areas; and 
 a plurality of connection lines spaced apart from each other and electrically connected to the gate driver, wherein in each of the plurality of pixel areas, at least one of the plurality of connection lines is electrically connected to at least one of the plurality of scan lines; 
   wherein lengths of the plurality of connection lines are gradually increased from a first side of the active switch array substrate to a second side of the active switch array substrate, and the plurality of connection lines are electrically connected to the plurality of scan lines, in sequential order, through the first side of the active switch array substrate, the first side is opposite to the second side;   wherein the active switch array substrate comprises a first conductive layer and a second conductive layer, the plurality of scan lines are disposed in the first conductive layer, the plurality of connection lines are disposed in the second conductive layer, conductive vias are formed at each location where one of the plurality of connection lines crosses one of the plurality of scan lines corresponding thereto, and the plurality of connection lines are electrically connected to the plurality of scan lines corresponding thereto, through the conductive vias, respectively.   
     
     
         5 . The display panel according to  claim 4 , wherein the source driver is disposed at a first end of the active switch array substrate, the gate driver is disposed at a second end of the active switch array substrate, and the second end is opposite to the first end. 
     
     
         6 . The display panel according to  claim 4 , wherein a plurality of connection lines are disposed in parallel with each other. 
     
     
         7 . The display panel according to  claim 4 , wherein the plurality of connection lines and the plurality of data lines are disposed in parallel with each other. 
     
     
         8 . The display panel according to  claim 4 , wherein each of the plurality of connection lines is disposed between two adjacent data lines. 
     
     
         9 . The display panel according to  claim 4 , wherein a plurality of connection lines are disposed in parallel with each other;
 wherein the plurality of connection lines and the plurality of data lines are disposed in parallel with each other;   wherein each of the plurality of connection lines is disposed between two adjacent data lines.   
     
     
         10 . The display panel according to  claim 4 , wherein the plurality of data lines comprise a first data line and a second data line adjacent to each other, the plurality of connection line comprises a first connection line, the plurality of scan lines comprises a first scan line, the active switch array substrate comprises a first active switch and a first pixel, the first active switch is coupled to the first scan line, the first data line and the first pixel, the first active switch and the first pixel are disposed between the first data line and the second data line, the first connection line is electrically connected to the first scan line, the first connection line is disposed between the first pixel and the second data line. 
     
     
         11 . The display panel according to  claim 4 , wherein the active switch array substrate comprises a plurality of common lines, and the plurality of connection lines cover on the plurality of common lines. 
     
     
         12 . The display panel according to  claim 4 , wherein the active switch array substrate comprises a first active switch and a common line, the first active switch is coupled to the common line, and a pixel capacitor and a storage capacitor are formed between the first active switch and the common line. 
     
     
         13 . The display panel according to  claim 5 , wherein the gate driver comprises a vertical shift register circuit, and the vertical shift register circuit is disposed at the first end of the active switch array substrate. 
     
     
         14 . The display panel according to  claim 4 , wherein the source driver is disposed at a first end of the active switch array substrate, the gate driver is disposed at a second end of the active switch array substrate, and the second end is opposite to the first end;
 wherein the gate driver comprises a vertical shift register circuit disposed at the first end of the active switch array substrate.   
     
     
         15 . The display panel according to  claim 4 , wherein a pin of the source driver is bonded to an edge of the active switch array substrate. 
     
     
         16 . The display panel according to  claim 4 , wherein a length of the gate driver is shorter than or equal to a width of the display area of the display panel. 
     
     
         17 . The display panel according to  claim 4 , wherein the gate driver is disposed at the top of the active switch array substrate, and the source driver is at the bottom of the active switch array substrate.