US2020286907A1PendingUtilityA1

Three-dimensional memory device with mobility-enhanced vertical channels and methods of forming the same

Assignee: SANDISK TECHNOLOGIES LLCPriority: Jan 18, 2019Filed: May 26, 2020Published: Sep 10, 2020
Est. expiryJan 18, 2039(~12.5 yrs left)· nominal 20-yr term from priority
H10D 64/693H10D 64/691H10D 64/033H10D 30/6893H10D 30/701H10D 30/69H10D 30/796H10D 30/63H10D 64/037H01L 29/42332H01L 29/792H01L 27/1159H01L 27/11568H01L 29/78391H01L 29/517H01L 29/518H01L 29/40111H10B 43/27H10B 51/30H10B 43/30
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Claims

Abstract

A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A three-dimensional memory device comprising:
 an alternating stack of insulating layers and electrically conductive layers overlying a substrate;   a memory opening fill structure that vertically extends through the alternating stack, wherein the memory opening fill structure comprises a memory film, a vertical semiconductor channel, and a core structure comprising a polycrystalline core material, wherein the polycrystalline core material induces a lateral compressive strain and a vertical tensile strain to the vertical semiconductor channel.   
     
     
         2 . The three-dimensional memory device of  claim 1 , wherein:
 the polycrystalline core material is a phase change material including an amorphous phase having a first density and a polycrystalline phase having a second density that is less than the first density;   the polycrystalline core material is in the polycrystalline phase of the phase change material; and   the second density is in a range from 90% of the first density to 98% of the first density.   
     
     
         3 . The three-dimensional memory device of  claim 1 , wherein:
 the polycrystalline core material has electrical conductivity less than 1.0×10 −5  S/m; and   the core structure has a vertical-to-lateral dimension ratio in a range from 3 to 300.   
     
     
         4 . The three-dimensional memory device of  claim 1 , wherein:
 the vertical semiconductor channel is under lateral compressive strain having a magnitude in a range from 0.1% to 2.0%; and   the vertical semiconductor channel is under vertical tensile strain having a magnitude in a range from 0.01% to 0.2%.   
     
     
         5 . The three-dimensional memory device of  claim 2 , wherein the core material includes a compound comprising germanium, tellurium, and oxygen. 
     
     
         6 . The three-dimensional memory device of  claim 5 , wherein the core material comprises oxygen at an atomic percentage in a range from 6.0% to 14%. 
     
     
         7 . The three-dimensional memory device of  claim 1 , wherein:
 the three-dimensional memory device comprises a two-dimensional array of NAND strings vertically extending through the alternating stack, wherein the memory opening fill structure comprises one of the NAND strings;   the electrically conductive layers comprise, or are electrically connected to, a respective word line for the two-dimensional array of NAND strings;   the substrate comprises a silicon substrate;   at least one memory cell in a first device level of the two-dimensional array of NAND strings is located over another memory cell in a second device level of two-dimensional array of NAND strings;   the electrically conductive layers comprise a plurality of control gate electrodes for the two-dimensional array of NAND strings,   the electrically conductive layers have a respective strip shape extending substantially parallel to the top surface of the substrate; and   each NAND string within the two-dimensional array of NAND strings comprises a respective memory film, a respective vertical semiconductor channel, and a respective core structure.

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