Software-transparent hardware predictor for core-to-core data transfer optimization

Abstract

Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

1 .- 29 . (canceled) 
     
     
         30 . An apparatus comprising:
 a set of counters to track accesses and/or demotions of a subset of a plurality of cache lines stored in a first core's private cache, each counter corresponds to one of a plurality of cores and tracks a number of accesses and/or demotions that are associated with a corresponding core;   target core determination circuitry to determine, from the plurality of cores, one or more target cores based on one or more counter values tracked by the set of counters; and   enablement circuitry to enable a cache line push operation to push at least one of the plurality of cache lines from the first core's private cache to the one or more target cores' private cache.   
     
     
         31 . The apparatus of  claim 30 , wherein for each access or demotion of the cache lines in the subset, the counter corresponding to the core with which the access or the demotion is associated, is incremented. 
     
     
         32 . The apparatus of  claim 31 , wherein for each access or demotion of the cache lines in the subset, each of the counters that corresponds to a core that is not associated with the access or the demotion, is decremented. 
     
     
         33 . The apparatus of  claim 30 , wherein the plurality of cache lines are demotion candidates to be demoted from the first core's private cache to a lower level cache responsive to one or more executions of a cache line demotion operation by the first core, the lower level cache shared by the first core and at least one of the plurality of cores. 
     
     
         34 . The apparatus of  claim 33 , wherein the cache lines in the subset are not to be demoted to the lower level cache or pushed to the one or more target cores' private cache. 
     
     
         35 . The apparatus of  claim 30 , wherein an occurrence of one or more triggering events is to cause the target core determination circuitry to determine the one or more target cores. 
     
     
         36 . The apparatus of  claim 35 , wherein the apparatus further comprises a detection counter to track a total number of the accesses and/or the demotions to the cache lines in the subset, and wherein the one or more triggering events comprise the total number of the accesses and/or the demotions tracked by the detection counter reaching a maximum threshold. 
     
     
         37 . The apparatus of  claim 35 , wherein the apparatus further comprises a timer, and the one or more triggering events comprise an expiration of the timer. 
     
     
         38 . The apparatus of  claim 35 , wherein the one or more triggering events comprise a counter value of any one of the counters in the set of counters reaching an individual maximum threshold. 
     
     
         39 . The apparatus of  claim 35 , wherein the one or more triggering events comprise a counter value of any one of the counters in the set of counters reaching an individual minimum threshold. 
     
     
         40 . The apparatus of  claim 35 , wherein upon the occurrence of one or more triggering events, the target core determination circuitry is to determine a subset of counters from the set of counters, each counter in the subset having a counter value within a specific range, and wherein a subset of the plurality of cores which corresponds to the subset of counters is selected by the target core determination circuitry as the target cores. 
     
     
         41 . The apparatus as in  claim 40 , wherein when there is only one target core, the at least one of the plurality of cache lines is pushed to the target core's private cache via direct cache-to-cache transfer or via prefetch hints provided to a prefetcher of the one or more target core. 
     
     
         42 . The apparatus as in  claim 40 , wherein when there is more than one target core, the at least one of the plurality of cache lines is multi-casted to each of the target cores. 
     
     
         43 . A method comprising:
 tracking, via a set of counters, accesses and/or demotions of a subset of a plurality of cache lines stored in a first core's private cache, wherein each counter in the set corresponds to one of a plurality of cores and tracks a number of accesses and/or demotions that are associated with a corresponding core;   determining, from the plurality of cores, one or more target cores based on one or more counter values tracked by the set of counters; and   executing a cache line push operation to push at least one of the plurality of cache lines from the first core's private cache to the one or more target cores' private cache.   
     
     
         44 . The method of  claim 43 , further comprising:
 incrementing, for each access or demotion of the cache lines in the subset, the counter corresponding to the core with which the access or the demotion is associated.   
     
     
         45 . The method of  claim 44 , further comprising:
 decrementing, for each access or demotion of the cache lines in the subset, each of the counters that corresponds to a core that is not associated with the access or the demotion.   
     
     
         46 . The method of  claim 43 , wherein the plurality of cache lines are demotion candidates to be demoted from the first core's private cache to a lower level cache responsive to one or more executions of a cache line demotion operation by the first core, the lower level cache shared by the first core and at least one of the plurality of cores. 
     
     
         47 . The method of  claim 46 , wherein the cache lines in the subset are not to be demoted to the lower level cache or pushed to the one or more target cores' private cache. 
     
     
         48 . The method of  claim 43 , further comprising:
 detecting an occurrence of one or more triggering events and responsively causing the determining of the one or more target cores.   
     
     
         49 . The method of  claim 48 , further comprising:
 tracking a total number of the accesses and/or the demotions to the cache lines in the subset, and wherein the one or more triggering events comprise the total number of the accesses and/or the demotions reaching a maximum threshold.   
     
     
         50 . The method of  claim 48 , wherein the one or more triggering events comprise an expiration of a timer. 
     
     
         51 . The method of  claim 48 , wherein the one or more triggering events comprise a counter value of any one of the counters in the set of counters reaching an individual maximum threshold. 
     
     
         52 . The method of  claim 48 , wherein the one or more triggering events comprise a counter value of any one of the counters in the set of counters reaching an individual minimum threshold. 
     
     
         53 . The method of  claim 48 , further comprising:
 determining a subset of counters from the set of counters upon the occurrence of one or more triggering events, wherein each counter in the subset comprising a counter value within a specific range; and   selecting a subset of the plurality of cores which corresponds to the subset of counters as the target cores.   
     
     
         54 . The method as in  claim 53 , further comprising:
 when the one or more target cores comprise only one target core, pushing the at least one of the plurality of cache lines to the target core's private cache via direct cache-to-cache transfer or via prefetch hints provided to a prefetcher of the target core.   
     
     
         55 . The method as in  claim 53 , further comprising:
 when the one or more target cores comprise more than one target core, multi-casting the at least one of the plurality of cache lines to each of the target cores.