Lateral Semiconductor Power Devices

Abstract

Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.

1 - 20 . (canceled) 
     
     
         21 . A lateral power semiconductor device, comprising:
 an n-type source region;   a p-type body region, and a gate electrode which is capacitively coupled to a portion of the body region;   an n-type drain region;   an n-type drift region, which is laterally interposed between the drain region and the body region in an electrical relation such that, when the gate electrode has a positive voltage which inverts part of the body region to form a channel therein, electrons can flow from the source region, through the channel, laterally through the drift region, and to the drain region;   wherein the source, body, drift, and drain regions are all located within a mass of p-type semiconductor material; and   p-type charge balancing regions which laterally flank the drift region, and which are laterally flanked by insulating trenches which include immobile positive electrostatic charge; and   wherein, when reverse bias is present between the source and drain regions, the negative space charge of depleted portions of the p-type charge balancing regions, will at least partially balance the positive space charge of depleted portions of the drift region in combination with the fixed charge in the trenches   
     
     
         22 . The lateral power semiconductor device of  claim 21 , wherein the semiconductor substrate is monolithic silicon. 
     
     
         23 . The lateral power semiconductor device of  claim 21 , further comprising a p-type top semiconductor layer which overlies the drift region. 
     
     
         24 . The lateral power semiconductor device of  claim 21 , wherein the semiconductor substrate is a semiconductor-on-insulator structure. 
     
     
         25 . The lateral power semiconductor device of  claim 21 , wherein the gate is insulated from the body region by a thin dielectric layer. 
     
     
         26 . The lateral power semiconductor device of  claim 21 , wherein the drift region overlaps a total width of the gate electrode at an interface between the body region and the drift region. 
     
     
         27 . A power semiconductor device, comprising, on a single die, multiple lateral power transistors which each include:
 a first-conductivity-type source region;   a second-conductivity-type body region, and a gate electrode which is capacitively coupled to a portion of the body region;   a first-conductivity-type drain region;   a first-conductivity-type drift region, which is laterally interposed between the drain region and the body region in an electrical relation such that, when the gate electrode has a voltage which inverts part of the body region to form a channel therein, majority carriers can flow from the source region, through the channel, laterally through the drift region, to the drain region;   wherein the source, body, drift, and drain regions are all located within a mass of second-conductivity-type semiconductor material; and   second-conductivity-type charge balancing regions which laterally flank the drift region, and which are laterally flanked by insulating trenches;   wherein, when reverse bias is present between the source and drain regions, the space charge of depleted portions of the second-conductivity-type charge balancing regions and of the upper region will at least partially balance the space charge of depleted portions of the drift region;   and wherein the respective drain regions of the multiple transistors are isolated from each other by intervening portions of the second-conductivity-type mass of semiconductor material.   
     
     
         28 . The power semiconductor device of  claim 27 , wherein the first conductivity type is n-type, and the second conductivity type is p-type. 
     
     
         29 . The power semiconductor device of  claim 27 , wherein the semiconductor substrate is monolithic silicon. 
     
     
         30 . The power semiconductor device of  claim 27 , wherein the semiconductor substrate is a semiconductor-on-insulator structure. 
     
     
         31 . The power semiconductor device of  claim 27 , wherein the gate is insulated from the body region by a thin dielectric layer. 
     
     
         32 . The power semiconductor device of  claim 27 , wherein the drift region overlaps a total width of the gate electrode at an interface between the body region and the drift region. 
     
     
         33 . A lateral power semiconductor device, comprising:
 a first-conductivity-type source region;   a second-conductivity-type body region, and a gate electrode which is capacitively coupled to a portion of the body region;   a first-conductivity-type drain region;   a first-conductivity-type drift region, which is laterally interposed between the drain region and the body region in an electrical relation such that, when the gate electrode has a voltage which inverts part of the body region to form a channel therein, majority carriers can flow from the source region, through the channel, through the drift region, to the drain region;   wherein the source, body, drift, and drain regions are all located within a second-conductivity type well, which overlies a first-conductivity-type buried layer, which in turn overlies a mass of second-conductivity-type semiconductor material;   second-conductivity-type charge balancing regions which laterally flank the drift region, and which are laterally flanked by insulating trenches; and   wherein, when reverse bias is present between the source and drain regions, the space charge of depleted portions of the second-conductivity-type charge balancing regions will at least partially balance the space charge of depleted portions of the drift region.   
     
     
         34 . The lateral power semiconductor device of  claim 33 , wherein the first conductivity type is n-type, and the second conductivity type is p-type. 
     
     
         35 . The lateral power semiconductor device of  claim 33 , wherein the semiconductor substrate is monolithic silicon. 
     
     
         36 . The lateral power semiconductor device of  claim 33 , wherein the semiconductor substrate is a semiconductor-on-insulator structure. 
     
     
         37 . The lateral power semiconductor device of  claim 33 , wherein the gate is insulated from the body region by a thin dielectric layer. 
     
     
         38 . The lateral power semiconductor device of  claim 33 , wherein the drift region overlaps a total width of the gate electrode at an interface between the body region and the drift region. 
     
     
         39 - 51 . (canceled)