Dynamic Memory Supporting Simultaneous Refresh and Data-Access Transactions

Abstract

Described are dynamic memory systems that perform overlapping refresh and data access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

1 . A memory controller to control an external, multi-bank memory device integrated circuit including a plurality of banks, the memory controller comprising:
 a scheduler circuit to generate memory requests such that a refresh operation is performed in a first bank from the plurality of banks included in the multi-bank memory device integrated circuit while a memory access operation is performed in a second bank from the plurality of banks included in the multi-bank memory device integrated circuit;   a request interface to transmit the memory requests to the multi-bank memory device integrated circuit.   
     
     
         2 . The memory controller of  claim 1 , wherein the scheduler includes a data access transaction generator that generated the memory access transaction performed in the second bank. 
     
     
         3 . The memory controller of  claim 1 , further comprising:
 memory to store a row-based indication of memory cells that have been refreshed in the multi-bank memory device integrated circuit at least within a current refresh interval.   
     
     
         4 . The memory controller of  claim 3 , wherein the scheduler further includes:
 a refresh transaction generator to generate refresh operations for memory cells in the multi-bank memory device integrated circuit while refraining from generating refresh operations for the memory cells that have been refreshed within the current refresh interval, the refresh operations including the refresh operation for the first bank of the multi-bank memory device integrated circuit that is not pending a memory access operation.   
     
     
         5 . The memory controller of  claim 1 , further comprising:
 a queue to store an indication of banks of the multi-bank memory device integrated circuit subject to pending memory access operations and refresh operations, the indication including the memory access operation for the second bank of the multi-bank memory device integrated circuit, and the refresh operation of the first bank of the multi-bank memory device integrated circuit that is not pending a memory access operation.   
     
     
         6 . The memory controller of  claim 1 , further comprising:
 a transaction combiner to organize bank-specific commands including the memory access operation for the second bank and the refresh operation for the first bank into a combined command, the request interface to transmit the memory requests as the combined command to the multi-bank memory device integrated circuit.   
     
     
         7 . The memory controller of  claim 1 , wherein the memory access operation for the second bank and the refresh operation for the first bank are executed simultaneously. 
     
     
         8 . The memory controller integrated circuit of  claim 5 , further comprising:
 conflict circuitry to reorganize the pending memory access operations and the refresh operations to prevent at least one memory access operation and at least one refresh operation from being contemporaneously issued to a same bank of the multi-bank memory device integrated circuit.   
     
     
         9 . The memory controller of  claim 8 , wherein the conflict circuitry reorganizes the pending memory access operations and the refresh operations by inserting a delay field into the at least one memory access operation or the at least one refresh operation, wherein an execution of the at least one memory access operation or the at least one refresh operation is delayed by the multi-bank memory device integrated circuit based on the delay field. 
     
     
         10 . A method of a memory controller to control an external, multi-bank memory device integrated circuit including a plurality of banks, the method controller comprising:
 generating memory requests such that a refresh operation is performed in a first bank from the plurality of banks included in the multi-bank memory device integrated circuit while a memory access operation is performed in a second bank from the plurality of banks included in the multi-bank memory device integrated circuit;   transmitting the memory requests to the multi-bank memory device integrated circuit.   
     
     
         11 . The method of  claim 10 , further comprising:
 storing in a memory of the memory controller a row-based indication of memory cells that have been refreshed in the multi-bank memory device integrated circuit at least within a current refresh interval.   
     
     
         12 . The method of  claim 11 , further comprising:
 generating refresh operations for memory cells in the multi-bank memory device integrated circuit while refraining from generating refresh operations for the memory cells that have been refreshed within the current refresh interval, the refresh operations including the refresh operation for the first bank of the multi-bank memory device integrated circuit that is not pending a memory access operation.   
     
     
         13 . The method of  claim 10 , further comprising:
 storing an indication of banks of the multi-bank memory device integrated circuit subject to pending memory access operations and refresh operations, the indication including the memory access operation for the second bank of the multi-bank memory device integrated circuit, and the refresh operation of the first bank of the multi-bank memory device integrated circuit that is not pending a data access transaction.   
     
     
         14 . The method of  claim 10 , further comprising:
 organizing bank-specific commands including the memory access operation for the second bank and the refresh operation for the first bank into a combined command,   wherein the memory requests are transmitted as the combined command to the multi-bank memory device integrated circuit.   
     
     
         15 . The method of  claim 10 , wherein the memory access operation for the second bank and the refresh operation for the first bank are executed simultaneously. 
     
     
         16 . The method of  claim 13 , further comprising:
 reorganizing the pending memory access operations and the refresh operations to prevent at least one memory access operation and at least one refresh operation from being contemporaneously issued to a same bank of the multi-bank memory device integrated circuit.   
     
     
         17 . The method of  claim 16 , wherein reorganizing the pending memory access operations and the refresh operations comprises inserting a delay field into the at least one memory access operation or the at least one refresh operation, wherein an execution of the at least one memory access operation or the at least one refresh operation is delayed by the multi-bank memory device integrated circuit based on the delay field. 
     
     
         18 . A memory controller to control an external, multi-bank memory device integrated circuit including a plurality of banks, the memory controller comprising:
 a means for generating memory requests such that a refresh operation is performed in a first bank from the plurality of banks included in the multi-bank memory device integrated circuit while a memory access operation is performed in a second bank from the plurality of banks included in the multi-bank memory device integrated circuit;   a means for transmitting the memory requests to the multi-bank memory device integrated circuit.   
     
     
         19 . The memory controller of  claim 18 , further comprising:
 a means for storing a row-based indication of memory cells that have been refreshed in the multi-bank memory device integrated circuit at least within a current refresh interval.   
     
     
         20 . The memory controller of  claim 19 , further comprising:
 a means for generating refresh operations for memory cells in the multi-bank memory device integrated circuit while refraining from generating refresh operations for the memory cells that have been refreshed within the current refresh interval, the refresh operations including the refresh operation for the first bank of the multi-bank memory device integrated circuit that is not pending a memory access operation.