Semiconductor package structure and method for manufacturing the same

Abstract

A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.

What is claimed is: 
     
         1 . A substrate structure, comprising:
 a conductive layer having an upper surface; and   a multi-layered circuit structure and a protection layer disposed on the upper surface of the conductive layer, wherein an upper surface of the multi-layered circuit structure is lower than an upper surface of the protection layer.   
     
     
         2 . The substrate structure of  claim 1 , further comprising a solder bump directly disposed on the upper surface of the multi-layered circuit structure. 
     
     
         3 . The substrate structure of  claim 2 , wherein the protection layer defines a through hole to expose a portion of the multi-layered circuit structure, and the solder bump is disposed on and contacts the portion of the multi-layered circuit structure. 
     
     
         4 . The substrate structure of  claim 1 , wherein the multi-layered circuit structure comprises a barrier layer and a wetting layer disposed on the barrier layer. 
     
     
         5 . The substrate structure of  claim 4 , wherein the barrier layer is disposed on and contacts the upper surface of the conductive layer. 
     
     
         6 . The substrate structure of  claim 4 , wherein a material of the barrier layer comprises nickel, and a material of the wetting layer comprises palladium or gold. 
     
     
         7 . The substrate structure of  claim 1 , wherein the multi-layered circuit structure contacts the upper surface of the conductive layer, and the protection layer contacts the upper surface of the multi-layered circuit structure. 
     
     
         8 . The substrate structure of  claim 1 , wherein the multi-layered circuit structure consists of a plurality of layers, and peripheral walls of the layers align with each other. 
     
     
         9 . The substrate structure of  claim 1 , wherein the protection layer covers the peripheral walls of each of the layers of the multi-layered circuit structure. 
     
     
         10 . The substrate structure of  claim 1 , further comprising an insulating layer having a side surface, wherein the conductive layer and the protection layer are disposed on the insulating layer, and the protection layer has a side surface that is not coplanar with the side surface of the first insulating layer. 
     
     
         11 . The substrate structure of  claim 10 , wherein the insulating layer defines a first through hole extending through the first insulating layer, the first conductive layer has a conductive pad disposed in the first through hole, the multi-layered circuit structure comprises a bonding region disposed on the conductive pad, and the solder bump is directly disposed on the bonding region of the multi-layered circuit structure 
     
     
         12 . The substrate structure of  claim 1 , wherein a layout of the multi-layered circuit structure is the same as a layout of the conductive layer. 
     
     
         13 . The substrate structure of  claim 1 , wherein the multi-layered circuit structure has as substantially consistent thickness. 
     
     
         14 . A semiconductor package structure, comprising:
 a conductive layer having an upper surface;   a multi-layered circuit structure and a protection layer disposed on the upper surface of the conductive layer, wherein an upper surface of the multi-layered circuit structure is lower than an upper surface of the protection layer; and   a semiconductor chip electrically connected to the multi-layered circuit structure.   
     
     
         15 . The semiconductor package structure of  claim 14 , further comprising at least one solder bump connecting the semiconductor chip and the multi-layered circuit structure. 
     
     
         16 . The semiconductor package structure of  claim 15 , wherein the solder bump is directly disposed on the upper surface of the multi-layered circuit structure. 
     
     
         17 . The semiconductor package structure of  claim 16 , wherein the protection layer defines a through hole to expose a portion of the multi-layered circuit structure, and the solder bump is disposed on and contacts the portion of the multi-layered circuit structure. 
     
     
         18 . The semiconductor package structure of  claim 17 , further comprising an encapsulant encapsulating the semiconductor chip and the solder bump, and a portion of the encapsulant is disposed between a surface of the solder bump and a side wall of the through hole of the protection layer. 
     
     
         19 . The substrate structure of  claim 14 , wherein the multi-layered circuit structure comprises a barrier layer and a wetting layer disposed on the barrier layer. 
     
     
         20 . The semiconductor package structure of  claim 19 , wherein a material of the barrier layer comprises nickel, and a material of the wetting layer comprises palladium or gold.