Sensing a memory cell

Abstract

Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.

1 . (canceled) 
     
     
         2 . A device, comprising:
 a memory cell configured to store a logic state;   a first capacitor configured to integrate a charge associated with the memory cell during a read operation;   a first cascode coupled with the memory cell and a first node; and   a second cascode coupled with the first capacitor and the first node, wherein the second cascode is configured to isolate the first node from the first capacitor based at least in part on a voltage of a digit line failing to satisfy a threshold.   
     
     
         3 . The device of  claim 2 , further comprising:
 a first transistor coupled with the first node and a sense component and configured to selectively couple the first node with the sense component during the read operation after the first capacitor is isolated from the first node.   
     
     
         4 . The device of  claim 2 , wherein the second cascode is configured to enable a sense window during the read operation based at least in part on the second cascode being coupled with the first capacitor and a sense component. 
     
     
         5 . The device of  claim 2 , further comprising:
 a second transistor coupled with the first capacitor and a second node of the second cascode, the second transistor is configured to precharge the first capacitor to a first voltage during the read operation.   
     
     
         6 . The device of  claim 2 , wherein the second cascode is configured to selectively isolate the first capacitor from the first node during the read operation. 
     
     
         7 . The device of  claim 2 , further comprising:
 a second capacitor coupled with the first node, wherein the second capacitor is configured to transfer an additional charge to the memory cell after the first capacitor is isolated from the memory cell.   
     
     
         8 . The device of  claim 7 , wherein the second capacitor comprises a parasitic capacitance at the first node. 
     
     
         9 . The device of  claim 7 , wherein at least the first node or the first capacitor is configured to discharge a first voltage with a first rate of change. 
     
     
         10 . The device of  claim 9 , wherein at least the first node or the second capacitor is configured to discharge a second voltage with a second rate of change, wherein the second rate of change is greater than the first rate of change. 
     
     
         11 . The device of  claim 10 , wherein the first rate of change and the second rate of change configure a sense window during the read operation. 
     
     
         12 . The device of  claim 2 , wherein the memory cell is configured to receive, when the memory cell stores a first logic state, a first amount of charge during the read operation that is greater than a second amount of charge received when the memory cell stores a second logic state. 
     
     
         13 . A method, comprising:
 transferring a charge associated with a memory cell between the memory cell and a capacitor through a first cascode and a second cascode during a read operation, the first cascode being coupled with the memory cell and a first node, and the second cascode being coupled with the capacitor and the first node;   isolating the first node from the capacitor based at least in part on transferring the charge and on a voltage of a digit line failing to satisfy a threshold;   coupling, using a transistor, the first node with a sense component after isolating the first node from the capacitor; and   determining a logic state stored on the memory cell based at least in part on coupling the first node with the sense component.   
     
     
         14 . The method of  claim 13 , further comprising:
 coupling the memory cell to the digit line that has been charged to a first voltage; and   supplying the charge from the capacitor to the memory cell based at least in part on coupling the memory cell to the digit line.   
     
     
         15 . The method of  claim 14 , wherein the charge supplied from the capacitor is associated with the memory cell storing a first logic state, the charge being less than a second charge associated with the memory cell storing a second logic state. 
     
     
         16 . The method of  claim 13 , further comprising:
 isolating the capacitor from the memory cell by deactivating the second cascode based at least in part on transferring the charge between the memory cell and the capacitor.   
     
     
         17 . The method of  claim 16 , wherein deactivating the second cascode is based at least in part on a voltage across the capacitor being reduced during the read operation. 
     
     
         18 . The method of  claim 13 , further comprising:
 transferring an additional charge from the first node to the memory cell based at least in part on transferring the charge between the memory cell and the capacitor through.   
     
     
         19 . The method of  claim 13 , further comprising:
 coupling the memory cell to the first node based at least in part on biasing a word line, wherein the first node is configured to couple with the sense component; and   establishing a voltage that is indicative of the logic state stored on the memory cell at the first node based at least in part on coupling the memory cell to the first node.   
     
     
         20 . The method of  claim 19 , further comprising:
 deactivating the second cascode to isolate the first node from the capacitor based at least in part on establishing the voltage at the first node; and   activating the transistor positioned between the first node and the sense component to couple the first node with the sense component during the read operation based at least in part on deactivating the first cascode.   
     
     
         21 . A memory device, comprising:
 a memory array comprising a memory cell coupled with a digit line;   a controller coupled with the memory array and with a capacitor configured to integrate a charge associated with the memory cell during a read operation, the controller configured to cause the memory device:
 transfer the charge between the memory cell and the capacitor through a first cascode and a second cascode during the read operation, the first cascode being coupled with the memory cell and a first node, and the second cascode being coupled with the capacitor and the first node; 
 isolate the first node from the capacitor based at least in part on transferring the charge and on a voltage of the digit line failing to satisfy a threshold; 
 couple, using a transistor, the first node with a sense component after isolating the first node from the capacitor; and 
 determine a logic state stored on the memory cell based at least in part on coupling the first node with the sense component.