Differentiator circuit

Abstract

Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

What is claimed is: 
     
         1 . An analog-to-digital converter (ADC), comprising:
 a filter having an input and an output;   a delta-sigma modulator having an input and an output; and   a cascaded integrator comb (CIC) filter coupled to the filter and the delta-sigma modulator and comprising:
 a multiplexer having a first input, a second input, a control input, and an output; 
 a first register having an input coupled to the output of the multiplexer and an output; 
 a second register having an input coupled to the output of the first register and an output; 
 a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register; and 
 a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer. 
   
     
     
         2 . The ADC of  claim 1 , wherein the CIC filter further comprises:
 a first integrator having an input and an output; and   a second integrator having an input coupled to the output of the first integrator and an output.   
     
     
         3 . The ADC of  claim 2 , wherein the CIC filter further comprises:
 one or more additional integrators coupled between the first integrator and the second integrator; and   one or more additional registers coupled between the first register and the second register, wherein a number of the one or more additional registers is equal to a number of the one or more additional integrators.   
     
     
         4 . The ADC of  claim 2 , further comprising an up-sampler having an input coupled to the output of the third register and an output coupled to the input of the first integrator. 
     
     
         5 . The ADC of  claim 2 , further comprising a down-sampler having an input coupled to the output of the second integrator and an output coupled to the second input of the multiplexer. 
     
     
         6 . The ADC of  claim 2 , wherein the output of the delta-sigma modulator is coupled to the input of the first integrator, and wherein the output of the third register is coupled to the input of the filter. 
     
     
         7 . The ADC of  claim 2 , wherein the output of the filter is coupled to the second input of the multiplexer, and wherein the input of the delta-sigma modulator is coupled to the output of the second integrator. 
     
     
         8 . A analog-to-digital converter (ADC), comprising:
 a cascaded integrator comb (CIC) filter, comprising:
 a plurality of integrators coupled in series with a first of the plurality of integrators beginning the series and a second of the plurality of integrators ending the series; 
 a differentiator comprising:
 a multiplexer having a first input, a second input, a control input, and an output; 
 a first register having an input coupled to the output of the multiplexer and an output; 
 a second register having an input coupled to the output of the first register and an output; 
 a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register; and 
 a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer; and 
 
 a signal sampler having a first terminal coupled to one of the plurality of integrators and a second terminal coupled to the differentiator. 
   
     
     
         9 . The ADC of  claim 8 , wherein the signal sampler is a down-sampler having an input coupled to an output of the second of the plurality of integrators and an output coupled to the second input of the multiplexer. 
     
     
         10 . The ADC of  claim 8 , wherein the signal sampler is an up-sampler having an input coupled to an output of the third register and an output coupled to an input of the first of the plurality of integrators. 
     
     
         11 . The ADC of  claim 8 , wherein the differentiator comprises one or more additional registers coupled between the first register and the second register, wherein a number of the one or more additional registers equals one fewer than a number of the plurality of integrators. 
     
     
         12 . The ADC of  claim 8 , further comprising a delta-sigma modulator coupled to the CIC filter and a filter coupled to the CIC filter.